Commit | Line | Data |
---|---|---|
3f6eb730 MG |
1 | `define STATE_IDLE 2'd0 |
2 | `define STATE_LENGTH 2'd1 | |
3 | `define STATE_READ1 2'd2 | |
4 | `define STATE_READ2 2'd3 | |
5 | ||
6 | module READER (input clk, input clk_enable, input [7:0] uart_rx_byte, input uart_rx_signal, input uart_is_receiving, output reg active, output reg ram_we, output [12:0] ram_addr, output reg [15:0] ram_di); | |
7 | reg [1:0] state = `STATE_IDLE; | |
8 | ||
9 | reg [12:0] bytes_left = 0; | |
10 | reg [12:0] current_index = 0; | |
11 | ||
12 | assign ram_addr = current_index; | |
13 | ||
14 | always @ (posedge clk) | |
15 | if (clk_enable) begin | |
16 | if(!uart_rx_signal) ram_we <= 0; | |
17 | ||
18 | case(state) | |
19 | `STATE_IDLE: begin | |
20 | if(uart_rx_signal) begin | |
21 | bytes_left[12:8] <= uart_rx_byte[4:0]; | |
22 | bytes_left[7:0] <= 0; | |
23 | current_index <= -1; | |
24 | active <= 1; | |
25 | state <= `STATE_LENGTH; | |
26 | end else | |
27 | active <= 0; | |
28 | end | |
29 | ||
30 | `STATE_LENGTH: begin | |
31 | if(uart_rx_signal) begin | |
32 | bytes_left[7:0] <= uart_rx_byte; | |
33 | state <= `STATE_READ1; | |
34 | end | |
35 | end | |
36 | ||
37 | `STATE_READ1: begin | |
38 | if(uart_rx_signal) begin | |
39 | ram_di[15:8] <= uart_rx_byte; | |
40 | current_index <= current_index + 1; | |
41 | bytes_left <= bytes_left - 1; | |
42 | state <= `STATE_READ2; | |
43 | end | |
44 | end | |
45 | ||
46 | `STATE_READ2: begin | |
47 | if(uart_rx_signal) begin | |
48 | ram_di[7:0] <= uart_rx_byte; | |
49 | ram_we <= 1; | |
50 | state <= |bytes_left ? `STATE_READ1 : `STATE_IDLE; | |
51 | end | |
52 | end | |
53 | endcase | |
54 | end | |
55 | endmodule |