chip.v

   1 `define OP_NOP   3'd0
   2 `define OP_LOADA 3'd1
   3 `define OP_LOADB 3'd2
   4 `define OP_STORE 3'd3
   5 `define OP_READ  3'd4
   6 `define OP_LOADI 3'd5
   7 `define OP_ROUTE 3'd6
   8 `define OP_RUG   3'd7
   9
  10 module chip(input clk, input [2:0] op, input [15:0] I, input io_pin, input CS, output reg [15:0] mem_in, input [15:0] mem_out, output reg mem_write);
  11
  12    // parity is unimplemented
  13
  14    // OP_LOADA
  15    wire [2:0] flagr = I[2:0];
  16    wire           bsel = I[3];
  17    wire [7:0] aluc = I[11:4];
  18
  19    // OP_LOADB
  20    wire [2:0] cond = I[2:0];
  21    wire           inv = I[3];
  22    wire [7:0] alus = I[11:4];
  23
  24    // OP_STORE
  25    wire [2:0] flagw = I[2:0];
  26    wire           edge_ = I[7];
  27    wire [3:0] cube = I[11:8];
  28
  29    // OP_ROUTE
  30    wire [5:0] cycle = I[5:0];
  31    wire [1:0] check = I[7:6];
  32    wire [3:0] xor_  = I[11:8];
  33    wire [2:0] snarf = I[14:12];
  34    wire           odd   = I[15];
  35
  36    // OP_RUG
  37    wire           rw = I[0];
  38    wire           ac = I[1];
  39    wire           news = I[2];
  40    wire [4:0] reg_ = I[8:4];
  41
  42
  43    reg [15:0] A;
  44    reg [15:0] B;
  45    reg [15:0] C;
  46    reg [15:0] F;
  47    reg [15:0] Cond;
  48    reg [15:0] R;
  49    reg [7:0]  alu_sum;
  50    reg [7:0]  alu_carry;
  51    reg [15:0] cube_in;
  52    reg            io;
  53
  54    // these are not really regs
  55
  56    wire [15:0]  alu_sum_out;
  57    wire [15:0]  alu_carry_out;
  58
  59    wire [2:0]  alu_index [15:0];
  60
  61 assign alu_index[0] = (A[0] << 2) + (B[0] << 1) + F[0];
  62 assign alu_sum_out[0] = alu_sum[alu_index[0]];
  63 assign alu_carry_out[0] = alu_carry[alu_index[0]];
  64 assign alu_index[1] = (A[1] << 2) + (B[1] << 1) + F[1];
  65 assign alu_sum_out[1] = alu_sum[alu_index[1]];
  66 assign alu_carry_out[1] = alu_carry[alu_index[1]];
  67 assign alu_index[2] = (A[2] << 2) + (B[2] << 1) + F[2];
  68 assign alu_sum_out[2] = alu_sum[alu_index[2]];
  69 assign alu_carry_out[2] = alu_carry[alu_index[2]];
  70 assign alu_index[3] = (A[3] << 2) + (B[3] << 1) + F[3];
  71 assign alu_sum_out[3] = alu_sum[alu_index[3]];
  72 assign alu_carry_out[3] = alu_carry[alu_index[3]];
  73 assign alu_index[4] = (A[4] << 2) + (B[4] << 1) + F[4];
  74 assign alu_sum_out[4] = alu_sum[alu_index[4]];
  75 assign alu_carry_out[4] = alu_carry[alu_index[4]];
  76 assign alu_index[5] = (A[5] << 2) + (B[5] << 1) + F[5];
  77 assign alu_sum_out[5] = alu_sum[alu_index[5]];
  78 assign alu_carry_out[5] = alu_carry[alu_index[5]];
  79 assign alu_index[6] = (A[6] << 2) + (B[6] << 1) + F[6];
  80 assign alu_sum_out[6] = alu_sum[alu_index[6]];
  81 assign alu_carry_out[6] = alu_carry[alu_index[6]];
  82 assign alu_index[7] = (A[7] << 2) + (B[7] << 1) + F[7];
  83 assign alu_sum_out[7] = alu_sum[alu_index[7]];
  84 assign alu_carry_out[7] = alu_carry[alu_index[7]];
  85 assign alu_index[8] = (A[8] << 2) + (B[8] << 1) + F[8];
  86 assign alu_sum_out[8] = alu_sum[alu_index[8]];
  87 assign alu_carry_out[8] = alu_carry[alu_index[8]];
  88 assign alu_index[9] = (A[9] << 2) + (B[9] << 1) + F[9];
  89 assign alu_sum_out[9] = alu_sum[alu_index[9]];
  90 assign alu_carry_out[9] = alu_carry[alu_index[9]];
  91 assign alu_index[10] = (A[10] << 2) + (B[10] << 1) + F[10];
  92 assign alu_sum_out[10] = alu_sum[alu_index[10]];
  93 assign alu_carry_out[10] = alu_carry[alu_index[10]];
  94 assign alu_index[11] = (A[11] << 2) + (B[11] << 1) + F[11];
  95 assign alu_sum_out[11] = alu_sum[alu_index[11]];
  96 assign alu_carry_out[11] = alu_carry[alu_index[11]];
  97 assign alu_index[12] = (A[12] << 2) + (B[12] << 1) + F[12];
  98 assign alu_sum_out[12] = alu_sum[alu_index[12]];
  99 assign alu_carry_out[12] = alu_carry[alu_index[12]];
 100 assign alu_index[13] = (A[13] << 2) + (B[13] << 1) + F[13];
 101 assign alu_sum_out[13] = alu_sum[alu_index[13]];
 102 assign alu_carry_out[13] = alu_carry[alu_index[13]];
 103 assign alu_index[14] = (A[14] << 2) + (B[14] << 1) + F[14];
 104 assign alu_sum_out[14] = alu_sum[alu_index[14]];
 105 assign alu_carry_out[14] = alu_carry[alu_index[14]];
 106 assign alu_index[15] = (A[15] << 2) + (B[15] << 1) + F[15];
 107 assign alu_sum_out[15] = alu_sum[alu_index[15]];
 108 assign alu_carry_out[15] = alu_carry[alu_index[15]];
 109
 110    reg [2:0]   flags_addr;
 111
 112    always @* begin
 113           case(op)
 114                 `OP_LOADA:
 115                   flags_addr <= flagr;
 116                 `OP_LOADB:
 117                   flags_addr <= cond;
 118                 `OP_STORE:
 119                   flags_addr <= flagw;
 120                 default:
 121                   flags_addr <= 0;
 122           endcase
 123    end
 124
 125    wire [15:0] flags_in;
 126    reg  [15:0] flags_out;
 127    reg             flags_write;
 128
 129    RAM #(.ADDRESS_BITS(3)) flags (.clk(clk), .write(flags_write), .addr(flags_addr), .in(flags_in), .out(flags_out));
 130
 131    reg [15:0]  idx;
 132
 133    always @ (posedge clk) begin
 134           if(mem_write)
 135                 mem_write <= 0;
 136           if(flags_write)
 137                 flags_write <= 0;
 138
 139           case (op)
 140                 `OP_NOP: begin end
 141
 142                 `OP_LOADA:
 143                   begin
 144                          alu_carry <= aluc;
 145                          F <= flags_out;
 146                          A <= mem_out;
 147                          C <= mem_out;
 148                          io <= io_pin;
 149                          if (bsel)
 150                            B <= cube_in;
 151                   end
 152
 153                 `OP_LOADB:
 154                   begin
 155                          alu_sum <= alus;
 156                          Cond <= inv ? ~flags_out : flags_out;
 157                          B <= mem_out;
 158                          R <= mem_out;
 159                   end
 160
 161                 `OP_STORE:
 162                   begin
 163                          for(idx=0; idx < 16; idx++)
 164                            flags_in[idx] <= Cond[idx] ? alu_carry_out[idx] : flags_out[idx];
 165                          flags_write <= 1;
 166                          mem_in <= alu_sum_out;
 167                          mem_write <= 1;
 168                          // lots other stuff
 169                   end
 170
 171                 `OP_READ:
 172                   begin
 173                          if (CS)
 174                            mem_in <= mem_out;
 175                   end
 176
 177                 `OP_LOADI:
 178                   begin
 179                          C <= mem_out;
 180                          A <= I;
 181                          alu_sum <= 8'b11110000; // out of A, B, F, select exactly A
 182                   end
 183
 184 /*              `OP_RUG:
 185                   begin
 186                          if(!rw && ac && !news)
 187                            begin
 188                                   rug[reg_] <= A;
 189                                   C <= mem_out;
 190                            end
 191                          if(!rw && !ac && !news)
 192                            begin
 193                                   rug[reg_] <= C;
 194                                   A <= mem_out;
 195                            end
 196                          if(rw && ac && !news)
 197                            begin
 198                                   A <= rug[reg_];
 199                                   mem_in <= C;
 200                            end
 201                          if(rw && !ac && !news)
 202                            begin
 203                                   C <= rug[reg_];
 204                                   mem_in <= A;
 205                            end
 206                          if(rw && !ac && news)
 207                            begin
 208                                   R <= mem_out;
 209                                   cube_in <= mem_out;
 210                            end
 211                          if(rw && ac && news)
 212                            begin
 213                                   cube_in <= mem_out;
 214                            end
 215                   end
 216 */
 217           endcase
 218    end
 219 endmodule