10 module chip(input clk, input [2:0] op, input [15:0] I, input io_pin, input CS, output reg [15:0] mem_in, input [15:0] mem_out, output reg mem_write);
12 // parity is unimplemented
15 wire [2:0] flagr = I[2:0];
17 wire [7:0] aluc = I[11:4];
20 wire [2:0] cond = I[2:0];
22 wire [7:0] alus = I[11:4];
25 wire [2:0] flagw = I[2:0];
27 wire [3:0] cube = I[11:8];
30 wire [5:0] cycle = I[5:0];
31 wire [1:0] check = I[7:6];
32 wire [3:0] xor_ = I[11:8];
33 wire [2:0] snarf = I[14:12];
40 wire [4:0] reg_ = I[8:4];
54 // these are not really regs
56 wire [15:0] alu_sum_out;
57 wire [15:0] alu_carry_out;
59 wire [2:0] alu_index [15:0];
61 assign alu_index[0] = (A[0] << 2) + (B[0] << 1) + F[0];
62 assign alu_sum_out[0] = alu_sum[alu_index[0]];
63 assign alu_carry_out[0] = alu_carry[alu_index[0]];
64 assign alu_index[1] = (A[1] << 2) + (B[1] << 1) + F[1];
65 assign alu_sum_out[1] = alu_sum[alu_index[1]];
66 assign alu_carry_out[1] = alu_carry[alu_index[1]];
67 assign alu_index[2] = (A[2] << 2) + (B[2] << 1) + F[2];
68 assign alu_sum_out[2] = alu_sum[alu_index[2]];
69 assign alu_carry_out[2] = alu_carry[alu_index[2]];
70 assign alu_index[3] = (A[3] << 2) + (B[3] << 1) + F[3];
71 assign alu_sum_out[3] = alu_sum[alu_index[3]];
72 assign alu_carry_out[3] = alu_carry[alu_index[3]];
73 assign alu_index[4] = (A[4] << 2) + (B[4] << 1) + F[4];
74 assign alu_sum_out[4] = alu_sum[alu_index[4]];
75 assign alu_carry_out[4] = alu_carry[alu_index[4]];
76 assign alu_index[5] = (A[5] << 2) + (B[5] << 1) + F[5];
77 assign alu_sum_out[5] = alu_sum[alu_index[5]];
78 assign alu_carry_out[5] = alu_carry[alu_index[5]];
79 assign alu_index[6] = (A[6] << 2) + (B[6] << 1) + F[6];
80 assign alu_sum_out[6] = alu_sum[alu_index[6]];
81 assign alu_carry_out[6] = alu_carry[alu_index[6]];
82 assign alu_index[7] = (A[7] << 2) + (B[7] << 1) + F[7];
83 assign alu_sum_out[7] = alu_sum[alu_index[7]];
84 assign alu_carry_out[7] = alu_carry[alu_index[7]];
85 assign alu_index[8] = (A[8] << 2) + (B[8] << 1) + F[8];
86 assign alu_sum_out[8] = alu_sum[alu_index[8]];
87 assign alu_carry_out[8] = alu_carry[alu_index[8]];
88 assign alu_index[9] = (A[9] << 2) + (B[9] << 1) + F[9];
89 assign alu_sum_out[9] = alu_sum[alu_index[9]];
90 assign alu_carry_out[9] = alu_carry[alu_index[9]];
91 assign alu_index[10] = (A[10] << 2) + (B[10] << 1) + F[10];
92 assign alu_sum_out[10] = alu_sum[alu_index[10]];
93 assign alu_carry_out[10] = alu_carry[alu_index[10]];
94 assign alu_index[11] = (A[11] << 2) + (B[11] << 1) + F[11];
95 assign alu_sum_out[11] = alu_sum[alu_index[11]];
96 assign alu_carry_out[11] = alu_carry[alu_index[11]];
97 assign alu_index[12] = (A[12] << 2) + (B[12] << 1) + F[12];
98 assign alu_sum_out[12] = alu_sum[alu_index[12]];
99 assign alu_carry_out[12] = alu_carry[alu_index[12]];
100 assign alu_index[13] = (A[13] << 2) + (B[13] << 1) + F[13];
101 assign alu_sum_out[13] = alu_sum[alu_index[13]];
102 assign alu_carry_out[13] = alu_carry[alu_index[13]];
103 assign alu_index[14] = (A[14] << 2) + (B[14] << 1) + F[14];
104 assign alu_sum_out[14] = alu_sum[alu_index[14]];
105 assign alu_carry_out[14] = alu_carry[alu_index[14]];
106 assign alu_index[15] = (A[15] << 2) + (B[15] << 1) + F[15];
107 assign alu_sum_out[15] = alu_sum[alu_index[15]];
108 assign alu_carry_out[15] = alu_carry[alu_index[15]];
110 reg [2:0] flags_addr;
125 wire [15:0] flags_in;
126 reg [15:0] flags_out;
129 RAM #(.ADDRESS_BITS(3)) flags (.clk(clk), .write(flags_write), .addr(flags_addr), .in(flags_in), .out(flags_out));
133 always @ (posedge clk) begin
156 Cond <= inv ? ~flags_out : flags_out;
163 for(idx=0; idx < 16; idx++)
164 flags_in[idx] <= Cond[idx] ? alu_carry_out[idx] : flags_out[idx];
166 mem_in <= alu_sum_out;
181 alu_sum <= 8'b11110000; // out of A, B, F, select exactly A
186 if(!rw && ac && !news)
191 if(!rw && !ac && !news)
196 if(rw && ac && !news)
201 if(rw && !ac && !news)
206 if(rw && !ac && news)