10 `define DIRECTION_N 3'd0
11 `define DIRECTION_NE 3'd1
12 `define DIRECTION_E 3'd2
13 `define DIRECTION_SE 3'd3
14 `define DIRECTION_S 3'd4
15 `define DIRECTION_SW 3'd5
16 `define DIRECTION_W 3'd6
17 `define DIRECTION_NW 3'd7
19 module chip(input clk, input [2:0] op, input [15:0] I, input io_pin, input CS, output reg [15:0] mem_in, input [15:0] mem_out, output reg mem_write);
21 // parity is unimplemented
24 wire [3:0] flagr = I[3:0];
26 wire [0:7] aluc = I[12:5];
29 wire [3:0] cond = I[3:0];
31 wire [0:7] alus = I[12:5];
34 wire [3:0] flagw = I[3:0];
36 wire [3:0] cube = I[11:8];
39 wire [5:0] cycle = I[5:0];
40 wire [1:0] check = I[7:6];
41 wire [3:0] xor_ = I[11:8];
42 wire [2:0] snarf = I[14:12];
49 wire [4:0] reg_ = I[8:4];
58 reg [7:0] alu_sum = 0;
59 reg [7:0] alu_carry = 0;
63 // these are not really regs
65 reg [15:0] alu_sum_out;
66 reg [15:0] alu_carry_out;
68 reg [2:0] alu_index [15:0];
73 for(idx = 0; idx < 16; idx=idx+1) begin
74 alu_index[idx] = (A[idx] << 2) + (B[idx] << 1) + F[idx];
75 alu_sum_out[idx] <= alu_sum[alu_index[idx]];
76 alu_carry_out[idx] <= alu_carry[alu_index[idx]];
80 reg [3:0] newstable[0:15][0:7];
100 newstable[2][1] = 15;
106 newstable[2][7] = 13;
107 newstable[3][0] = 15;
108 newstable[3][1] = 12;
114 newstable[3][7] = 14;
120 newstable[4][5] = 11;
126 newstable[5][3] = 10;
134 newstable[6][3] = 11;
135 newstable[6][4] = 10;
143 newstable[7][4] = 11;
144 newstable[7][5] = 10;
150 newstable[8][3] = 13;
151 newstable[8][4] = 12;
152 newstable[8][5] = 15;
153 newstable[8][6] = 11;
157 newstable[9][2] = 10;
158 newstable[9][3] = 14;
159 newstable[9][4] = 13;
160 newstable[9][5] = 12;
163 newstable[10][0] = 6;
164 newstable[10][1] = 7;
165 newstable[10][2] = 11;
166 newstable[10][3] = 15;
167 newstable[10][4] = 14;
168 newstable[10][5] = 13;
169 newstable[10][6] = 9;
170 newstable[10][7] = 5;
171 newstable[11][0] = 7;
172 newstable[11][1] = 4;
173 newstable[11][2] = 8;
174 newstable[11][3] = 12;
175 newstable[11][4] = 15;
176 newstable[11][5] = 14;
177 newstable[11][6] = 10;
178 newstable[11][7] = 6;
179 newstable[12][0] = 8;
180 newstable[12][1] = 9;
181 newstable[12][2] = 13;
182 newstable[12][3] = 1;
183 newstable[12][4] = 0;
184 newstable[12][5] = 3;
185 newstable[12][6] = 15;
186 newstable[12][7] = 11;
187 newstable[13][0] = 9;
188 newstable[13][1] = 10;
189 newstable[13][2] = 14;
190 newstable[13][3] = 2;
191 newstable[13][4] = 1;
192 newstable[13][5] = 0;
193 newstable[13][6] = 12;
194 newstable[13][7] = 8;
195 newstable[14][0] = 10;
196 newstable[14][1] = 11;
197 newstable[14][2] = 15;
198 newstable[14][3] = 3;
199 newstable[14][4] = 2;
200 newstable[14][5] = 1;
201 newstable[14][6] = 13;
202 newstable[14][7] = 9;
203 newstable[15][0] = 11;
204 newstable[15][1] = 8;
205 newstable[15][2] = 12;
206 newstable[15][3] = 0;
207 newstable[15][4] = 3;
208 newstable[15][5] = 2;
209 newstable[15][6] = 14;
210 newstable[15][7] = 10;
213 reg [3:0] flags_addr_latch;
214 reg [3:0] flags_addr;
218 flags_addr <= flags_addr_latch;
233 wire [15:0] flags_out;
236 reg [15:0] latest_news;
238 RAM #(.ADDRESS_BITS(3)) flags (.clk(clk), .write(flags_write), .addr(flags_addr[2:0]), .in(flags_in), .out(flags_out));
240 reg [15:0] flag_or_news;
245 if(flags_addr[3]) begin // read from news
246 for(idx = 0; idx < 16; idx++) begin
247 newsidx = newstable[idx][flags_addr[2:0]];
248 flag_or_news[idx] = latest_news[newsidx];
251 flag_or_news = flags_out;
255 always @ (posedge clk) begin
258 if(flags_write) begin
260 flags_addr_latch <= 0;
280 Cond <= inv ? ~flag_or_news : flag_or_news;
287 for(idx = 0; idx < 16; idx++) begin
288 flags_in[idx] = Cond[idx] ? alu_carry_out[idx] : flags_out[idx];
289 latest_news[idx] <= flags_in[idx];
291 if(flags_addr) begin // we do not write to flag 0
293 flags_addr_latch <= flags_addr;
295 mem_in <= alu_sum_out;
309 alu_sum <= 8'b11110000; // out of A, B, F, select exactly A
314 if(!rw && ac && !news)
319 if(!rw && !ac && !news)
324 if(rw && ac && !news)
329 if(rw && !ac && !news)
334 if(rw && !ac && news)