eval.v

   1 module EVAL(input clk, input clk_enable, input rst, input [15:0] Ein, output [15:0] Eout, output [3:0] gcop, output [5:0] ostate, output eval_finished, input conn_ea, input conn_et);
   2    reg [22:0] rom_output;
   3    reg [5:0]  eostate;
   4    reg [5:0]  enstate;
   5
   6 `ifdef SIM
   7    initial eostate <= 0;
   8 `endif
   9
  10    assign eval_finished = rom_output[22];
  11    wire et_lit = rom_output[21];
  12    wire ea_lit = rom_output[20];
  13    wire eaz_etz_eqv_disp = rom_output[19];
  14    wire et_disp = rom_output[18];
  15    wire rdC = rom_output[17];
  16    wire rdL = rom_output[16];
  17    wire rdN = rom_output[15];
  18    wire rdXp = rom_output[14];
  19    wire rdX = rom_output[13];
  20    wire rdV = rom_output[12];
  21    wire ldC = rom_output[11];
  22    wire ldL = rom_output[10];
  23    wire ldN = rom_output[9];
  24    wire ldX = rom_output[8];
  25    wire ldV = rom_output[7];
  26    assign gcop = rom_output[6:3];
  27    wire [2:0] lit = rom_output[2:0];
  28
  29    wire           et_zero = ~|E[15:13];
  30    wire           ea_zero = ~|E[12:0];
  31
  32    always @* begin
  33           case(eostate)
  34                 6'o00:   begin rom_output <= 23'o14004002; enstate <= 6'o01; end
  35                 6'o01:   begin rom_output <= 23'o14001000; enstate <= 6'o33; end
  36                 6'o02:   begin rom_output <= 23'o02040200; enstate <= 6'o23; end
  37                 6'o03:   begin rom_output <= 23'o00400120; enstate <= 6'o20; end
  38                 6'o04:   begin rom_output <= 23'o00010110; enstate <= 6'o64; end
  39                 6'o05:   begin rom_output <= 23'o00001170; enstate <= 6'o22; end
  40                 6'o06:   begin rom_output <= 23'o14000013; enstate <= 6'o71; end
  41                 6'o07:   begin rom_output <= 23'o00000000 | (1 << 22); enstate <= 6'o07; end
  42                 6'o10:   begin rom_output <= 23'o00020200; enstate <= 6'o45; end
  43                 6'o11:   begin rom_output <= 23'o00020200; enstate <= 6'o45; end
  44                 6'o12:   begin rom_output <= 23'o00100140; enstate <= 6'o02; end
  45                 6'o13:   begin rom_output <= 23'o00020200; enstate <= 6'o45; end
  46                 6'o14:   begin rom_output <= 23'o00020010; enstate <= 6'o53; end
  47                 6'o15:   begin rom_output <= 23'o00020010; enstate <= 6'o03; end
  48                 6'o16:   begin rom_output <= 23'o14002000; enstate <= 6'o40; end
  49                 6'o17:   begin rom_output <= 23'o00020010; enstate <= 6'o30; end
  50                 6'o20:   begin rom_output <= 23'o00100110; enstate <= 6'o21; end
  51                 6'o21:   begin rom_output <= 23'o10004161; enstate <= 6'o61; end
  52                 6'o22:   begin rom_output <= 23'o00004030; enstate <= 6'o24; end
  53                 6'o23:   begin rom_output <= 23'o00010500; enstate <= 6'o02; end
  54                 6'o24:   begin rom_output <= 23'o02010070; enstate <= 6'o33; end
  55                 6'o25:   begin rom_output <= 23'o00000040; enstate <= 6'o26; end
  56                 6'o26:   begin rom_output <= 23'o00010120; enstate <= 6'o30; end
  57                 6'o27:   begin rom_output <= 23'o00000240; enstate <= 6'o45; end
  58                 6'o30:   begin rom_output <= 23'o00000350; enstate <= 6'o45; end
  59                 6'o31:   begin rom_output <= 23'o00001150; enstate <= 6'o32; end
  60                 6'o32:   begin rom_output <= 23'o02200010; enstate <= 6'o63; end
  61                 6'o33:   begin rom_output <= 23'o01000440; enstate <= 6'o10; end
  62                 6'o34:   begin rom_output <= 23'o00201000; enstate <= 6'o35; end
  63                 6'o35:   begin rom_output <= 23'o00010020; enstate <= 6'o62; end
  64                 6'o36:   begin rom_output <= 23'o00400120; enstate <= 6'o54; end
  65                 6'o37:   begin rom_output <= 23'o01000430; enstate <= 6'o10; end
  66                 6'o40:   begin rom_output <= 23'o00020010; enstate <= 6'o36; end
  67                 6'o41:   begin rom_output <= 23'o00010020; enstate <= 6'o30; end
  68                 6'o42:   begin rom_output <= 23'o00010010; enstate <= 6'o30; end
  69                 6'o43:   begin rom_output <= 23'o00200010; enstate <= 6'o25; end
  70                 6'o44:   begin rom_output <= 23'o02010000; enstate <= 6'o55; end
  71                 6'o45:   begin rom_output <= 23'o01400020; enstate <= 6'o04; end
  72                 6'o46:   begin rom_output <= 23'o00200200; enstate <= 6'o45; end
  73                 6'o47:   begin rom_output <= 23'o00010010; enstate <= 6'o31; end
  74                 6'o50:   begin rom_output <= 23'o00000060; enstate <= 6'o51; end
  75                 6'o51:   begin rom_output <= 23'o00004030; enstate <= 6'o52; end
  76                 6'o52:   begin rom_output <= 23'o01000450; enstate <= 6'o40; end
  77                 6'o53:   begin rom_output <= 23'o00100120; enstate <= 6'o70; end
  78                 6'o54:   begin rom_output <= 23'o00100110; enstate <= 6'o56; end
  79                 6'o55:   begin rom_output <= 23'o14000201; enstate <= 6'o45; end
  80                 6'o56:   begin rom_output <= 23'o00200110; enstate <= 6'o60; end
  81                 6'o57:   begin rom_output <= 23'o14000200; enstate <= 6'o45; end
  82                 6'o60:   begin rom_output <= 23'o10004160; enstate <= 6'o61; end
  83                 6'o61:   begin rom_output <= 23'o00020020; enstate <= 6'o62; end
  84                 6'o62:   begin rom_output <= 23'o01000550; enstate <= 6'o10; end
  85                 6'o63:   begin rom_output <= 23'o02000030; enstate <= 6'o63; end
  86                 6'o64:   begin rom_output <= 23'o00002150; enstate <= 6'o65; end
  87                 6'o65:   begin rom_output <= 23'o00400010; enstate <= 6'o66; end
  88                 6'o66:   begin rom_output <= 23'o00001040; enstate <= 6'o50; end
  89                 6'o67:   begin rom_output <= 23'o00100130; enstate <= 6'o34; end
  90                 6'o70:   begin rom_output <= 23'o10000363; enstate <= 6'o45; end
  91                 6'o71:   begin rom_output <= 23'o00010130; enstate <= 6'o07; end
  92                 default: begin rom_output <= 23'o00000000; enstate <= 6'o07; end
  93           endcase
  94    end // always @ *
  95
  96    always @ (posedge clk) begin
  97           if (rst)
  98                 eostate = 0;
  99           if (clk_enable) begin
 100                  eostate <=
 101                                    et_disp ? (enstate | E[15:13]) :
 102                                    eaz_etz_eqv_disp ? (enstate | {ea_zero, et_zero, 1'b0}) :
 103                                    enstate;
 104           end
 105    end
 106
 107    assign ostate = eostate;
 108
 109    reg [15:0] V;
 110    reg [15:0] X;
 111    reg [15:0] N;
 112    reg [15:0] L;
 113    reg [15:0] C;
 114
 115    wire [15:0] E;
 116
 117    wire [15:0] EfromV = rdV ? V : 0;
 118    wire [15:0] EfromX = rdX ? X : 0;
 119    wire [15:0] EfromXp = rdXp ? {X[15:13], X[12:0] + 1} : 0;
 120    wire [15:0] EfromN = rdN ? N : 0;
 121    wire [15:0] EfromL = rdL ? L : 0;
 122    wire [15:0] EfromC = rdC ? C : 0;
 123    wire [12:0] EAfromEin = conn_ea ? Ein[12:0] : 0;
 124    wire [2:0]  ETfromEin = conn_et ? Ein[15:13] : 0;
 125    wire [15:0] EfromEin  = {ETfromEin, EAfromEin};
 126    wire [12:0] EAfromLIT = ea_lit ? {8'b0, lit, 1'b0} : 0;
 127    wire [2:0]  ETfromLIT = et_lit ? lit : 0;
 128    wire [15:0] EfromLIT = {ETfromLIT, EAfromLIT};
 129
 130    assign E = EfromV | EfromX | EfromXp | EfromN | EfromL | EfromC | EfromLIT | EfromEin;
 131    assign Eout = EfromV | EfromX | EfromXp | EfromN | EfromL | EfromC | EfromLIT;
 132
 133    always @ (posedge clk) begin
 134           if (clk_enable) begin
 135                  if (ldV) V <= E;
 136                  if (ldX) X <= E;
 137                  if (ldN) N <= E;
 138                  if (ldL) L <= E;
 139                  if (ldC) C <= E;
 140           end
 141    end
 142 endmodule // EVAL