gc.v

   1 `include "gcram.v"
   2
   3 module GC (input clk, input clk_enable, input rst, input [15:0] Ein, output [15:0] Eout, input [3:0] gcop, output [5:0] ostate, output conn_et, output conn_ea, output step_eval, output ram_we, output [12:0] ram_addr, output [15:0] ram_di, input [15:0] ram_do);
   4    reg [15:0] rom_output;
   5    reg [5:0]  gostate;
   6    reg [5:0]  gnstate;
   7    reg [15:0] Ein_latched;
   8
   9    always @(posedge clk) begin
  10           if(rst)
  11                 Ein_latched <= 16'b0100000000000100; // initial value of E
  12           else if(clk_enable)
  13                 Ein_latched <= Ein;
  14    end
  15
  16    wire ga_zero_disp = rom_output[15];
  17    wire gcop_disp    = rom_output[14];
  18    assign ram_we     = rom_output[13];
  19    wire adr          = rom_output[12];
  20    wire rdR          = rom_output[11];
  21    wire rdQ          = rom_output[10];
  22    wire rdP_plus     = rom_output[9];
  23    wire rdP          = rom_output[8];
  24    wire ldS          = rom_output[7];
  25    wire ldR          = rom_output[6];
  26    wire ldQ          = rom_output[5];
  27    wire ldP          = rom_output[4];
  28    wire conn_i       = rom_output[3];
  29    assign conn_et    = rom_output[2];
  30    assign conn_ea    = rom_output[1];
  31    assign step_eval  = rom_output[0];
  32
  33    wire ga_zero = ~|G[12:0];
  34
  35    always @* begin
  36           case(gostate)
  37                 6'o00:   begin rom_output <= 16'o010242; gnstate <= 6'o01; end
  38                 6'o01:   begin rom_output <= 16'o000031; gnstate <= 6'o02; end
  39                 6'o02:   begin rom_output <= 16'o040000; gnstate <= 6'o20; end
  40                 6'o03:   begin rom_output <= 16'o000126; gnstate <= 6'o04; end
  41                 6'o04:   begin rom_output <= 16'o001200; gnstate <= 6'o05; end
  42                 6'o05:   begin rom_output <= 16'o002020 | (1 << 12); gnstate <= 6'o06; end
  43                 6'o06:   begin rom_output <= 16'o000051; gnstate <= 6'o02; end
  44                 6'o07:   begin rom_output <= 16'o002020; gnstate <= 6'o10; end
  45                 6'o10:   begin rom_output <= 16'o001200; gnstate <= 6'o11; end
  46                 6'o11:   begin rom_output <= 16'o004020; gnstate <= 6'o12; end
  47                 6'o12:   begin rom_output <= 16'o002100 | (1 << 12); gnstate <= 6'o13; end
  48                 6'o13:   begin rom_output <= 16'o000057; gnstate <= 6'o02; end
  49                 6'o14:   begin rom_output <= 16'o004020; gnstate <= 6'o04; end
  50                 6'o15:   begin rom_output <= 16'o000246; gnstate <= 6'o16; end
  51                 6'o16:   begin rom_output <= 16'o020001; gnstate <= 6'o02; end
  52                 6'o17:   begin rom_output <= 16'o002100; gnstate <= 6'o42; end
  53                 6'o20:   begin rom_output <= 16'o000001; gnstate <= 6'o02; end
  54                 6'o21:   begin rom_output <= 16'o010306; gnstate <= 6'o06; end
  55                 6'o22:   begin rom_output <= 16'o000440; gnstate <= 6'o03; end
  56                 6'o23:   begin rom_output <= 16'o012200; gnstate <= 6'o12; end
  57                 6'o24:   begin rom_output <= 16'o000500; gnstate <= 6'o07; end
  58                 6'o25:   begin rom_output <= 16'o004040; gnstate <= 6'o24; end
  59                 6'o26:   begin rom_output <= 16'o014200; gnstate <= 6'o06; end
  60                 6'o27:   begin rom_output <= 16'o000440; gnstate <= 6'o14; end
  61                 6'o30:   begin rom_output <= 16'o012300; gnstate <= 6'o06; end
  62                 6'o31:   begin rom_output <= 16'o111300; gnstate <= 6'o44; end
  63                 6'o32:   begin rom_output <= 16'o111300; gnstate <= 6'o40; end
  64                 6'o33:   begin rom_output <= 16'o014200; gnstate <= 6'o15; end
  65                 6'o34:   begin rom_output <= 16'o000047; gnstate <= 6'o02; end
  66                 6'o35:   begin rom_output <= 16'o002007; gnstate <= 6'o02; end
  67                 6'o36:   begin rom_output <= 16'o002003; gnstate <= 6'o02; end
  68                 6'o37:   begin rom_output <= 16'o014200; gnstate <= 6'o55; end
  69                 6'o40:   begin rom_output <= 16'o004020; gnstate <= 6'o17; end
  70                 6'o41:   begin rom_output <= 16'o000000; gnstate <= 6'o41; end
  71                 6'o42:   begin rom_output <= 16'o000206; gnstate <= 6'o47; end
  72                 6'o43:   begin rom_output <= 16'o000106; gnstate <= 6'o46; end
  73                 6'o44:   begin rom_output <= 16'o004020; gnstate <= 6'o43; end
  74                 6'o45:   begin rom_output <= 16'o000000; gnstate <= 6'o41; end
  75                 6'o46:   begin rom_output <= 16'o002200; gnstate <= 6'o47; end
  76                 6'o47:   begin rom_output <= 16'o020440; gnstate <= 6'o50; end
  77                 6'o50:   begin rom_output <= 16'o111200; gnstate <= 6'o52; end
  78                 6'o51:   begin rom_output <= 16'o021100; gnstate <= 6'o54; end
  79                 6'o52:   begin rom_output <= 16'o004200; gnstate <= 6'o51; end
  80                 6'o53:   begin rom_output <= 16'o000000; gnstate <= 6'o41; end
  81                 6'o54:   begin rom_output <= 16'o004021; gnstate <= 6'o02; end
  82                 6'o55:   begin rom_output <= 16'o002100; gnstate <= 6'o56; end
  83                 6'o56:   begin rom_output <= 16'o000050; gnstate <= 6'o57; end
  84                 6'o57:   begin rom_output <= 16'o004007; gnstate <= 6'o02; end
  85                 default: begin rom_output <= 16'o040000; gnstate <= 6'o20; end
  86           endcase; // case (gostate)
  87    end // always @ *
  88
  89    always @ (posedge clk) begin
  90           if(rst)
  91                 gostate <= 0;
  92           if(clk_enable)
  93                 gostate <=
  94                                   ga_zero_disp ? (gnstate | ga_zero) :
  95                                   gcop_disp ? (gnstate | gcop) :
  96                                   gnstate;
  97    end // always @ (posedge clk)
  98
  99    assign ostate = gostate;
 100
 101    reg [12:0] P;
 102    reg [15:0] Q;
 103    reg [15:0] R;
 104    reg [15:0] S;
 105
 106    reg [12:0] A; // latched address
 107
 108    assign ram_addr = A;
 109    assign ram_di = S;
 110
 111    wire [15:0] G;
 112    wire [15:0] Gout;
 113
 114    wire [15:0] GfromR = rdR ? R : 0;
 115    wire [15:0] GfromQ = rdQ ? Q : 0;
 116    wire [15:0] GfromP = rdP ? {3'b0, P} : 0;
 117    wire [15:0] GfromP_plus = rdP_plus ? {3'b0, P + 1} : 0;
 118    wire [15:0] GfromI = conn_i ? ram_do : 0;
 119    wire [12:0] GAfromE = conn_ea ? Ein_latched[12:0] : 0;
 120    wire [2:0] GTfromE = conn_et ? Ein_latched[15:13] : 0;
 121    wire [15:0] GfromE = {GTfromE, GAfromE};
 122
 123    assign G = GfromR | GfromQ | GfromP | GfromP_plus | GfromI | GfromE;
 124    assign Gout = GfromR | GfromQ | GfromP | GfromP_plus | GfromI;
 125
 126    assign Eout[12:0]  = conn_ea ? Gout[12:0]  : 0;
 127    assign Eout[15:13] = conn_et ? Gout[15:13] : 0;
 128
 129    always @ (posedge clk) begin
 130           if(clk_enable) begin
 131                  if (ldS) S = G;
 132                  if (ldP) P <= G[12:0];
 133                  if (ldR) R <= G;
 134                  if (ldQ) Q <= G;
 135                  if (adr) A <= S[12:0];
 136           end
 137    end
 138 endmodule // GC