2 `include "generic_fifo_sc_a.v"
9 `include "single_trigger.v"
16 `define GCOP_CDRQ 4'd3
17 `define GCOP_CARQ 4'd4
18 `define GCOP_CARR 4'd5
19 `define GCOP_CDRRX 4'd6
20 `define GCOP_CARRX 4'd7
21 `define GCOP_CDRQX 4'd8
22 `define GCOP_CONS 4'd9
23 `define GCOP_XCONS 4'd10
24 `define GCOP_RPLACDR 4'd11
25 `define GCOP_LDQ 4'd12
26 `define GCOP_RDQ 4'd13
27 `define GCOP_RDQA 4'd14
28 `define GCOP_RDQCDRRX 4'd15
33 `define UART_DIVIDE 625
36 module PROCESSOR (input clk, output [4:0] led, output uart_tx, input uart_rx);
39 reg [5:0] initial_reset = 30;
40 always @ (posedge clk)
41 if (initial_reset) initial_reset <= initial_reset - 1;
43 wire reset = |initial_reset || reader_active || writer_clock_enable;
44 reg [1:0] counter = 0;
46 wire gc_clock_enable = counter[0] & counter[1] & !reset;
47 wire eval_clock_enable = counter[0] & !counter[1] & step_eval & !reset;
48 wire writer_clock_enable = counter[0] & counter[1] & writer_active;
50 always @ (posedge clk)
51 counter <= counter + 1;
65 wire [12:0] gc_ram_addr;
66 wire [15:0] gc_ram_di;
69 wire [12:0] reader_ram_addr;
70 wire [15:0] reader_ram_di;
72 wire [12:0] writer_ram_addr;
76 wire ram_we = reader_active ? reader_ram_we : gc_ram_we;
77 wire [12:0] ram_addr = reader_active ? reader_ram_addr : writer_active ? writer_ram_addr : gc_ram_addr;
78 wire [15:0] ram_di = reader_active ? reader_ram_di : gc_ram_di;
82 reg writer_started = 0;
83 reg writer_active = 0;
85 GCRAM gcram (.clk(clk), .we(ram_we), .addr(ram_addr), .di(ram_di), .do(ram_do));
87 GC gc (.clk(clk), .rst(reset), .clk_enable(gc_clock_enable), .Ein(E1), .Eout(E2), .gcop(gcop), .ostate(gostate), .step_eval(step_eval), .conn_ea(conn_ea), .conn_et(conn_et), .ram_we(gc_ram_we), .ram_addr(gc_ram_addr), .ram_di(gc_ram_di), .ram_do(ram_do), .Pout(P));
89 EVAL eval (.clk(clk), .rst(reset), .clk_enable(eval_clock_enable), .Ein(E2), .Eout(E1), .gcop(gcop), .ostate(eostate), .conn_ea(conn_ea), .conn_et(conn_et));
91 READER reader (.clk(clk), .clk_enable(!initial_reset), .uart_rx_byte(uart_rx_byte), .uart_rx_signal(uart_rx_signal), .uart_is_receiving(uart_is_receiving), .active(reader_active), .ram_we(reader_ram_we), .ram_addr(reader_ram_addr), .ram_di(reader_ram_di));
93 WRITER writer (.clk(clk), .clk_enable(writer_clock_enable), .uart_tx_byte(uart_tx_byte), .uart_tx_signal(uart_tx_signal), .uart_is_transmitting(uart_is_transmitting), .finished(writer_finished), .ram_addr(writer_ram_addr), .ram_do(ram_do), .P(P));
97 wire [7:0] uart_rx_byte;
98 wire uart_is_receiving;
99 wire uart_is_transmitting;
104 wire [7:0] uart_tx_byte;
106 always @ (posedge clk) begin
110 if(reader_active) begin
112 end else if(eostate == 5'd7 && !writer_started) begin
119 uart #(.CLOCK_DIVIDE(`UART_DIVIDE)) uart (.clk(clk), .rx(uart_rx), .tx(uart_tx), .transmit(uart_tx_signal), .tx_byte(uart_tx_byte), .received(uart_rx_signal), .rx_byte(uart_rx_byte), .is_receiving(uart_is_receiving), .is_transmitting(uart_is_transmitting), .recv_error (uart_rx_error));
121 // Assign the outputs
122 assign led[0] = eval_clock_enable;
123 assign led[1] = uart_is_transmitting;
124 assign led[2] = uart_is_receiving;
125 assign led[4] = !reset;