lisp_processor.v

   1 `include "asciihex.v"
   2 `include "generic_fifo_sc_a.v"
   3 `include "gc.v"
   4 `include "eval.v"
   5 `include "ram.v"
   6 `include "rom.v"
   7 `include "prescaler.v"
   8 `include "single_trigger.v"
   9 `include "uart.v"
  10
  11 `define GCOP_NOP      4'd0
  12 `define GCOP_CDR      4'd1
  13 `define GCOP_CAR      4'd2
  14 `define GCOP_CDRQ     4'd3
  15 `define GCOP_CARQ     4'd4
  16 `define GCOP_CARR     4'd5
  17 `define GCOP_CDRRX    4'd6
  18 `define GCOP_CARRX    4'd7
  19 `define GCOP_CDRQX    4'd8
  20 `define GCOP_CONS     4'd9
  21 `define GCOP_XCONS    4'd10
  22 `define GCOP_RPLACDR  4'd11
  23 `define GCOP_LDQ      4'd12
  24 `define GCOP_RDQ      4'd13
  25 `define GCOP_RDQA     4'd14
  26 `define GCOP_RDQCDRRX 4'd15
  27
  28 module PROCESSOR (input clk, output [4:0] led, output uart_tx, input uart_rx);
  29    wire [15:0] result;
  30
  31    reg [5:0]   initial_reset = 30;
  32    always @ (posedge clk)
  33          if (initial_reset) initial_reset <= initial_reset - 1;
  34
  35    reg [1:0]  counter = 0;
  36
  37    wire gc_clock_enable   = counter[0] &  counter[1] & !initial_reset;
  38    wire eval_clock_enable = counter[0] & !counter[1] & step_eval & !initial_reset;
  39
  40    always @ (posedge clk)
  41          counter <= counter + 1;
  42
  43    wire [15:0] E1;
  44    wire [15:0] E2;
  45    wire [3:0] gcop;
  46    wire [5:0] gostate;
  47    wire [5:0] eostate;
  48    wire           conn_ea;
  49    wire           conn_et;
  50
  51    wire           step_eval;
  52
  53    wire        ram_we;
  54    wire [12:0] ram_addr;
  55    wire [15:0] ram_di;
  56    wire [15:0] ram_do;
  57
  58    GCRAM gcram (.clk(clk), .we(ram_we), .addr(ram_addr), .di(ram_di), .do(ram_do), .result(result));
  59
  60    GC gc (.clk(clk), .clk_enable(gc_clock_enable), .Ein(E1), .Eout(E2), .gcop(gcop), .ostate(gostate), .step_eval(step_eval), .conn_ea(conn_ea), .conn_et(conn_et), .ram_we(ram_we), .ram_addr(ram_addr), .ram_di(ram_di), .ram_do(ram_do));
  61
  62    EVAL eval (.clk(clk), .clk_enable(eval_clock_enable), .Ein(E2), .Eout(E1), .gcop(gcop), .ostate(eostate), .conn_ea(conn_ea), .conn_et(conn_et));
  63
  64    // UART outputs
  65    wire       uart_rx_signal;
  66    wire [7:0] uart_rx_byte;
  67    wire       uart_is_receiving;
  68    wire       uart_is_transmitting;
  69    wire       uart_rx_error;
  70
  71    // Input logic
  72    wire [3:0] fifo_in;
  73    wire [3:0] fifo_out;
  74    wire           fifo_full;
  75    wire           fifo_empty;
  76    wire           fifo_re = 0;//eval_clock & inst == `INST_READ & !fifo_empty;
  77    wire           fifo_we = uart_rx_signal & !fifo_full;
  78
  79    ascii_to_hex a2h (.ascii({1'b0, uart_rx_byte[6:0]}), .hex(fifo_in));
  80
  81    generic_fifo_sc_a #(.dw(4), .aw(4)) fifo
  82     (.clk(clk),
  83      .rst(1'b1),
  84      .re(fifo_re),
  85      .we(fifo_we),
  86      .din(fifo_in),
  87      .dout(fifo_out),
  88      .full(fifo_full),
  89      .empty(fifo_empty));
  90
  91    // UART logic
  92    reg       uart_tx_signal = 1;
  93    wire [7:0] uart_tx_byte = result[7:0];
  94
  95    // 300 baud uart
  96    uart #(.CLOCK_DIVIDE(39)) uart (.clk(clk), .rx(uart_rx), .tx(uart_tx), .transmit(uart_tx_signal), .tx_byte(uart_tx_byte), .received(uart_rx_signal), .rx_byte(uart_rx_byte), .is_receiving(uart_is_receiving), .is_transmitting(uart_is_transmitting), .recv_error (uart_rx_error));
  97
  98    // Assign the outputs
  99    assign led[0] = eval_clock;
 100    assign led[1] = uart_is_transmitting;
 101    assign led[2] = uart_is_receiving;
 102    assign led[3] = recv_error;
 103 endmodule