lisp_processor.v

   1 `include "asciihex.v"
   2 `include "generic_fifo_sc_a.v"
   3 `include "gc.v"
   4 `include "eval.v"
   5 `include "ram.v"
   6 `include "rom.v"
   7 `include "prescaler.v"
   8 `include "single_trigger.v"
   9 `include "uart.v"
  10
  11 `define GCOP_NOP      4'd0
  12 `define GCOP_CDR      4'd1
  13 `define GCOP_CAR      4'd2
  14 `define GCOP_CDRQ     4'd3
  15 `define GCOP_CARQ     4'd4
  16 `define GCOP_CARR     4'd5
  17 `define GCOP_CDRRX    4'd6
  18 `define GCOP_CARRX    4'd7
  19 `define GCOP_CDRQX    4'd8
  20 `define GCOP_CONS     4'd9
  21 `define GCOP_XCONS    4'd10
  22 `define GCOP_RPLACDR  4'd11
  23 `define GCOP_LDQ      4'd12
  24 `define GCOP_RDQ      4'd13
  25 `define GCOP_RDQA     4'd14
  26 `define GCOP_RDQCDRRX 4'd15
  27
  28 module PROCESSOR (input clk, output [4:0] led, output uart_tx, input uart_rx);
  29    wire [7:0] result;
  30
  31    reg [1:0]  counter = 0;
  32
  33    reg gc_clock = counter[1];
  34    wire eval_clock = !counter[1] & step_eval;
  35
  36    always @ (posedge clk)
  37          counter <= counter + 1;
  38
  39    wire [7:0] E1;
  40    wire [7:0] E2;
  41    wire [3:0] gcop;
  42    wire [5:0] gostate;
  43    wire [5:0] eostate;
  44    wire           conn_ea;
  45    wire           conn_et;
  46
  47    wire           step_eval;
  48
  49    GC gc (.clk(gc_clock), .mclk(clk), .Ein(E1), .Eout(E2), .gcop(gcop), .ostate(gostate), .step_eval(step_eval), .conn_ea(conn_ea), .conn_et(conn_et), .result(result));
  50
  51    EVAL eval (.clk(eval_clock), .mclk(clk), .Ein(E2), .Eout(E1), .gcop(gcop), .ostate(eostate), .conn_ea(conn_ea), .conn_et(conn_et));
  52
  53    // UART outputs
  54    wire       uart_rx_signal;
  55    wire [7:0] uart_rx_byte;
  56    wire       uart_is_receiving;
  57    wire       uart_is_transmitting;
  58    wire       uart_rx_error;
  59
  60    // Input logic
  61    wire [3:0] fifo_in;
  62    wire [3:0] fifo_out;
  63    wire           fifo_full;
  64    wire           fifo_empty;
  65    wire           fifo_re = 0;//eval_clock & inst == `INST_READ & !fifo_empty;
  66    wire           fifo_we = uart_rx_signal & !fifo_full;
  67
  68    ascii_to_hex a2h (.ascii({1'b0, uart_rx_byte[6:0]}), .hex(fifo_in));
  69
  70    generic_fifo_sc_a #(.dw(4), .aw(4)) fifo
  71     (.clk(clk),
  72      .rst(1'b1),
  73      .re(fifo_re),
  74      .we(fifo_we),
  75      .din(fifo_in),
  76      .dout(fifo_out),
  77      .full(fifo_full),
  78      .empty(fifo_empty));
  79
  80    // UART logic
  81    reg       uart_tx_signal = 1;
  82    wire [7:0] uart_tx_byte = result;
  83
  84    // 300 baud uart
  85    uart #(.CLOCK_DIVIDE(39)) uart (.clk(clk), .rx(uart_rx), .tx(uart_tx), .transmit(uart_tx_signal), .tx_byte(uart_tx_byte), .received(uart_rx_signal), .rx_byte(uart_rx_byte), .is_receiving(uart_is_receiving), .is_transmitting(uart_is_transmitting), .recv_error (uart_rx_error));
  86
  87    // Assign the outputs
  88    assign led[0] = eval_clock;
  89    assign led[1] = uart_is_transmitting;
  90    assign led[2] = uart_is_receiving;
  91    assign led[3] = recv_error;
  92 endmodule