lisp_processor.v

   1 `include "gc.v"
   2 `include "eval.v"
   3 `include "reader.v"
   4 `include "uart.v"
   5 `include "writer.v"
   6
   7 `define GCOP_NOP      4'd0
   8 `define GCOP_CDR      4'd1
   9 `define GCOP_CAR      4'd2
  10 `define GCOP_CDRQ     4'd3
  11 `define GCOP_CARQ     4'd4
  12 `define GCOP_CARR     4'd5
  13 `define GCOP_CDRRX    4'd6
  14 `define GCOP_CARRX    4'd7
  15 `define GCOP_CDRQX    4'd8
  16 `define GCOP_CONS     4'd9
  17 `define GCOP_XCONS    4'd10
  18 `define GCOP_RPLACDR  4'd11
  19 `define GCOP_LDQ      4'd12
  20 `define GCOP_RDQ      4'd13
  21 `define GCOP_RDQA     4'd14
  22 `define GCOP_RDQCDRRX 4'd15
  23
  24 `ifdef SIM
  25  `define UART_DIVIDE 1
  26 `else
  27  `define UART_DIVIDE 625
  28 `endif
  29
  30 module cpu (input clk, output [4:0] led, output uart_tx, input uart_rx);
  31    wire [15:0] result;
  32
  33    reg [5:0]   initial_reset = 30;
  34    always @ (posedge clk)
  35          if (initial_reset) initial_reset <= initial_reset - 1;
  36
  37    wire reset = |initial_reset || reader_active || writer_clock_enable;
  38    reg [1:0]  counter = 0;
  39
  40    wire gc_clock_enable   = counter[0] &  counter[1] & !reset;
  41    wire eval_clock_enable = counter[0] & !counter[1] & step_eval & !reset;
  42    wire writer_clock_enable = counter[0] & counter[1] & writer_active;
  43
  44    always @ (posedge clk)
  45          counter <= counter + 1;
  46
  47    wire [12:0] P;
  48    wire [15:0] E1;
  49    wire [15:0] E2;
  50    wire [3:0] gcop;
  51    wire [5:0] gostate;
  52    wire [5:0] eostate;
  53    wire           conn_ea;
  54    wire           conn_et;
  55
  56    wire           step_eval;
  57
  58    wire        gc_ram_we;
  59    wire [12:0] gc_ram_addr;
  60    wire [15:0] gc_ram_di;
  61
  62    wire        reader_ram_we;
  63    wire [12:0] reader_ram_addr;
  64    wire [15:0] reader_ram_di;
  65
  66    wire [12:0] writer_ram_addr;
  67
  68    wire            reader_active;
  69
  70    wire        ram_we = reader_active ? reader_ram_we : gc_ram_we;
  71    wire [12:0] ram_addr = reader_active ? reader_ram_addr : writer_active ? writer_ram_addr : gc_ram_addr;
  72    wire [15:0] ram_di = reader_active ? reader_ram_di : gc_ram_di;
  73    wire [15:0] ram_do;
  74
  75    wire            writer_finished;
  76    reg             writer_started = 0;
  77    reg             writer_active = 0;
  78
  79    GCRAM gcram (.clk(clk), .we(ram_we), .addr(ram_addr), .di(ram_di), .do(ram_do));
  80
  81    GC gc (.clk(clk), .rst(reset), .clk_enable(gc_clock_enable), .Ein(E1), .Eout(E2), .gcop(gcop), .ostate(gostate), .step_eval(step_eval), .conn_ea(conn_ea), .conn_et(conn_et), .ram_we(gc_ram_we), .ram_addr(gc_ram_addr), .ram_di(gc_ram_di), .ram_do(ram_do), .Pout(P));
  82
  83    EVAL eval (.clk(clk), .rst(reset), .clk_enable(eval_clock_enable), .Ein(E2), .Eout(E1), .gcop(gcop), .ostate(eostate), .conn_ea(conn_ea), .conn_et(conn_et));
  84
  85    READER reader (.clk(clk), .clk_enable(!initial_reset), .rx_byte(uart_rx_byte), .rx_signal(uart_rx_signal), .active(reader_active), .ram_we(reader_ram_we), .ram_addr(reader_ram_addr), .ram_di(reader_ram_di));
  86
  87    WRITER writer (.clk(clk), .clk_enable(writer_clock_enable), .tx_byte(uart_tx_byte), .tx_signal(uart_tx_signal), .tx_busy(uart_is_transmitting), .finished(writer_finished), .ram_addr(writer_ram_addr), .ram_do(ram_do), .P(P));
  88
  89    // UART outputs
  90    wire       uart_rx_signal;
  91    wire [7:0] uart_rx_byte;
  92    wire       uart_is_receiving;
  93    wire       uart_is_transmitting;
  94    wire       uart_rx_error;
  95
  96    // UART logic
  97    wire           uart_tx_signal;
  98    wire [7:0] uart_tx_byte;
  99
 100    always @ (posedge clk) begin
 101           if(writer_finished)
 102                 writer_active <= 0;
 103
 104           if(reader_active) begin
 105                  writer_started <= 0;
 106           end else if(eostate == 5'd7 && !writer_started) begin
 107                  writer_started <= 1;
 108                  writer_active <= 1;
 109           end
 110    end
 111
 112    // 4800 baud uart
 113    uart #(.CLOCK_DIVIDE(`UART_DIVIDE)) uart (.clk(clk), .rx(uart_rx), .tx(uart_tx), .transmit(uart_tx_signal), .tx_byte(uart_tx_byte), .received(uart_rx_signal), .rx_byte(uart_rx_byte), .is_receiving(uart_is_receiving), .is_transmitting(uart_is_transmitting), .recv_error (uart_rx_error));
 114
 115    // Assign the outputs
 116    assign led[0] = eval_clock_enable;
 117    assign led[1] = uart_is_transmitting;
 118    assign led[2] = uart_is_receiving;
 119    assign led[3] = writer_finished;
 120    assign led[4] = !reset;
 121 endmodule