lisp_processor.v

   1 `include "asciihex.v"
   2 `include "generic_fifo_sc_a.v"
   3 `include "gc.v"
   4 `include "eval.v"
   5 `include "ram.v"
   6 `include "reader.v"
   7 `include "rom.v"
   8 `include "prescaler.v"
   9 `include "single_trigger.v"
  10 `include "uart.v"
  11 `include "writer.v"
  12
  13 `define GCOP_NOP      4'd0
  14 `define GCOP_CDR      4'd1
  15 `define GCOP_CAR      4'd2
  16 `define GCOP_CDRQ     4'd3
  17 `define GCOP_CARQ     4'd4
  18 `define GCOP_CARR     4'd5
  19 `define GCOP_CDRRX    4'd6
  20 `define GCOP_CARRX    4'd7
  21 `define GCOP_CDRQX    4'd8
  22 `define GCOP_CONS     4'd9
  23 `define GCOP_XCONS    4'd10
  24 `define GCOP_RPLACDR  4'd11
  25 `define GCOP_LDQ      4'd12
  26 `define GCOP_RDQ      4'd13
  27 `define GCOP_RDQA     4'd14
  28 `define GCOP_RDQCDRRX 4'd15
  29
  30 `ifdef SIM
  31  `define UART_DIVIDE 1
  32 `else
  33  `define UART_DIVIDE 625
  34 `endif
  35
  36 module PROCESSOR (input clk, output [4:0] led, output uart_tx, input uart_rx);
  37    wire [15:0] result;
  38
  39    reg [5:0]   initial_reset = 30;
  40    always @ (posedge clk)
  41          if (initial_reset) initial_reset <= initial_reset - 1;
  42
  43    wire reset = |initial_reset || reader_active || writer_clock_enable;
  44    reg [1:0]  counter = 0;
  45
  46    wire gc_clock_enable   = counter[0] &  counter[1] & !reset;
  47    wire eval_clock_enable = counter[0] & !counter[1] & step_eval & !reset;
  48    wire writer_clock_enable = counter[0] & counter[1] & writer_active;
  49
  50    always @ (posedge clk)
  51          counter <= counter + 1;
  52
  53    wire [12:0] P;
  54    wire [15:0] E1;
  55    wire [15:0] E2;
  56    wire [3:0] gcop;
  57    wire [5:0] gostate;
  58    wire [5:0] eostate;
  59    wire           conn_ea;
  60    wire           conn_et;
  61
  62    wire           step_eval;
  63
  64    wire        gc_ram_we;
  65    wire [12:0] gc_ram_addr;
  66    wire [15:0] gc_ram_di;
  67
  68    wire        reader_ram_we;
  69    wire [12:0] reader_ram_addr;
  70    wire [15:0] reader_ram_di;
  71
  72    wire [12:0] writer_ram_addr;
  73
  74    wire            reader_active;
  75
  76    wire        ram_we = reader_active ? reader_ram_we : gc_ram_we;
  77    wire [12:0] ram_addr = reader_active ? reader_ram_addr : writer_active ? writer_ram_addr : gc_ram_addr;
  78    wire [15:0] ram_di = reader_active ? reader_ram_di : gc_ram_di;
  79    wire [15:0] ram_do;
  80
  81    wire            writer_finished;
  82    reg             writer_started = 0;
  83    reg             writer_active = 0;
  84
  85    GCRAM gcram (.clk(clk), .we(ram_we), .addr(ram_addr), .di(ram_di), .do(ram_do));
  86
  87    GC gc (.clk(clk), .rst(reset), .clk_enable(gc_clock_enable), .Ein(E1), .Eout(E2), .gcop(gcop), .ostate(gostate), .step_eval(step_eval), .conn_ea(conn_ea), .conn_et(conn_et), .ram_we(gc_ram_we), .ram_addr(gc_ram_addr), .ram_di(gc_ram_di), .ram_do(ram_do), .Pout(P));
  88
  89    EVAL eval (.clk(clk), .rst(reset), .clk_enable(eval_clock_enable), .Ein(E2), .Eout(E1), .gcop(gcop), .ostate(eostate), .conn_ea(conn_ea), .conn_et(conn_et));
  90
  91    READER reader (.clk(clk), .clk_enable(!initial_reset), .uart_rx_byte(uart_rx_byte), .uart_rx_signal(uart_rx_signal), .uart_is_receiving(uart_is_receiving), .active(reader_active), .ram_we(reader_ram_we), .ram_addr(reader_ram_addr), .ram_di(reader_ram_di));
  92
  93    WRITER writer (.clk(clk), .clk_enable(writer_clock_enable), .uart_tx_byte(uart_tx_byte), .uart_tx_signal(uart_tx_signal), .uart_is_transmitting(uart_is_transmitting), .finished(writer_finished), .ram_addr(writer_ram_addr), .ram_do(ram_do), .P(P));
  94
  95    // UART outputs
  96    wire       uart_rx_signal;
  97    wire [7:0] uart_rx_byte;
  98    wire       uart_is_receiving;
  99    wire       uart_is_transmitting;
 100    wire       uart_rx_error;
 101
 102    // UART logic
 103    wire           uart_tx_signal;
 104    wire [7:0] uart_tx_byte;
 105
 106    always @ (posedge clk) begin
 107           if(writer_finished)
 108                 writer_active <= 0;
 109
 110           if(reader_active) begin
 111                  writer_started <= 0;
 112           end else if(eostate == 5'd7 && !writer_started) begin
 113                  writer_started <= 1;
 114                  writer_active <= 1;
 115           end
 116    end
 117
 118    // 4800 baud uart
 119    uart #(.CLOCK_DIVIDE(`UART_DIVIDE)) uart (.clk(clk), .rx(uart_rx), .tx(uart_tx), .transmit(uart_tx_signal), .tx_byte(uart_tx_byte), .received(uart_rx_signal), .rx_byte(uart_rx_byte), .is_receiving(uart_is_receiving), .is_transmitting(uart_is_transmitting), .recv_error (uart_rx_error));
 120
 121    // Assign the outputs
 122    assign led[0] = eval_clock_enable;
 123    assign led[1] = uart_is_transmitting;
 124    assign led[2] = uart_is_receiving;
 125    assign led[4] = !reset;
 126 endmodule