1 module RAM #(parameter ADDRESS_BITS = 4)
2 (input clk, input write, input[ADDRESS_BITS-1:0] addr, input [63:0] in, output reg [63:0] out);
4 reg [63:0] memory [0:2**ADDRESS_BITS-1];
6 reg [ADDRESS_BITS:0] idx;
8 for(idx = 0; idx < 2**ADDRESS_BITS; idx=idx+1)
12 always @ (negedge clk) begin