ram.v

   1 module RAM #(parameter ADDRESS_BITS = 4)
   2 (input clk, input write, input[ADDRESS_BITS-1:0] addr, input [15:0] in, output reg [15:0] out);
   3
   4     reg [15:0] memory [0:2**ADDRESS_BITS-1];
   5
   6     always @ (negedge clk) begin
   7         if (write)
   8                   memory[addr] <= in;
   9         out <= memory[addr];
  10     end
  11 endmodule