1 `define STATE_IDLE 2'd0
2 `define STATE_LENGTH 2'd1
3 `define STATE_READ1 2'd2
4 `define STATE_READ2 2'd3
6 module READER (input clk, input clk_enable, input [7:0] rx_byte, input rx_signal, output reg active, output reg ram_we, output [12:0] ram_addr, output reg [15:0] ram_di);
7 reg [1:0] state = `STATE_IDLE;
9 reg [12:0] words_left = 0;
10 reg [12:0] current_index = 0;
12 assign ram_addr = current_index;
14 always @ (posedge clk)
16 if(!rx_signal) ram_we <= 0;
21 words_left[12:8] <= rx_byte[4:0];
25 state <= `STATE_LENGTH;
32 words_left[7:0] <= rx_byte;
33 state <= `STATE_READ1;
39 ram_di[15:8] <= rx_byte;
40 current_index <= current_index + 1;
41 words_left <= words_left - 1;
42 state <= `STATE_READ2;
48 ram_di[7:0] <= rx_byte;
50 state <= |words_left ? `STATE_READ1 : `STATE_IDLE;