1 `define STATE_IDLE 2'd0
2 `define STATE_LENGTH 2'd1
3 `define STATE_READ1 2'd2
4 `define STATE_READ2 2'd3
6 module READER (input clk, input clk_enable, input [7:0] rx_byte, input rx_signal, output reg finished = 0, output reg ram_we, output [12:0] ram_addr, output reg [15:0] ram_di);
7 reg [1:0] state = `STATE_IDLE;
9 reg [12:0] total_words;
10 reg [12:0] current_index;
12 assign ram_addr = current_index;
14 always @ (posedge clk)
16 if(!rx_signal) ram_we <= 0;
21 total_words[12:8] <= rx_byte[4:0];
23 state <= `STATE_LENGTH;
29 total_words[7:0] <= rx_byte;
30 state <= `STATE_READ1;
36 ram_di[15:8] <= rx_byte;
37 current_index <= current_index + 1;
38 state <= `STATE_READ2;
44 ram_di[7:0] <= rx_byte;
46 if(current_index == total_words) begin
47 state <= `STATE_READ1;
55 end // if (clk_enable)