single_trigger.v

   1 // Take variable duration pulse which may be high at any time and generate a single cycle
   2 // high pulse alligned with the positive edge of the clock pulse.
   3
   4 module SINGLE_TRIGGER (input clk, input trigger_in, output trigger_out);
   5
   6    reg trigger = 0;
   7
   8    reg last_trigger_in = 0;
   9
  10    always @ (posedge clk) begin
  11
  12       if (!last_trigger_in & trigger_in)
  13          trigger <= 1;
  14       else
  15          trigger <= 0;
  16
  17       last_trigger_in <= trigger_in;
  18
  19    end
  20
  21    assign trigger_out = trigger;
  22
  23 endmodule