toplevel.v

   1 `include "master.v"
   2 `include "worker.v"
   3
   4 module toplevel (input CLKin, output [4:0] led);
   5    wire worker_tx;
   6    wire worker_rx;
   7
   8    wire worker_ready;
   9    wire master_ready;
  10
  11    wire [4:0] worker_led;
  12    wire [4:0] master_led;
  13
  14    worker worker (.CLKin(CLKin), .led(worker_led), .uart_tx(worker_tx), .uart_rx(worker_rx), .ready_out(worker_ready), .ready_in(master_ready));
  15
  16    master master (.CLKin(CLKin), .led(master_led), .uart_tx(worker_rx), .uart_rx(worker_tx), .ready_out(master_ready), .ready_in(worker_ready));
  17
  18    assign led = worker_led | master_led;
  19 endmodule