10 // s/192/3/ for 19200 baud uart
13 module worker (input CLKin, output [4:0] led, output uart_tx, input uart_rx, output reg ready_out = 1, input ready_in);
17 //pll pll (.clock_in(CLKin), .clock_out(clk));
19 reg [20:0] counter = 0;
23 always @ (posedge CLKin) begin
24 if(counter == 5000) begin
29 counter <= counter + 1;
37 RAM #(.ADDRESS_BITS(8)) ram (.clk(clk), .write(mem_write), .addr(mem_addr), .in(mem_in), .out(mem_out));
39 reg [7:0] from_uart [3:0];
40 reg [2:0] uart_ptr = 0;
42 wire [15:0] I = {from_uart[1], from_uart[0]};
43 assign mem_addr = from_uart[2];
44 wire [2:0] op_from_uart = from_uart[3][2:0];
45 wire CS = from_uart[3][3];
47 /* to execute a ROUTE instruction, we send our neighbour a STOREI
48 /* instruction with the correct address and value. This is the
49 /* STOREI instruction. */
50 wire [7:0] route_storei [3:0];
51 assign route_storei[0] = mem_out[7:0];
52 assign route_storei[1] = mem_out[15:8];
53 assign route_storei[2] = from_uart[0];
54 assign route_storei[3] = 3'd4; // OP_STOREI
58 reg [2:0] last_op = 0;
65 chip chip (.clk(clk), .op(op), .I(I), .io_pin(0), .CS(CS), .mem_in(mem_in), .mem_out(mem_out), .mem_write(mem_write), .led_out(led_out));
70 reg [7:0] tx_byte = 0;
74 // 19200 (actually 300) baud uart
75 uart #(.CLOCK_DIVIDE(`UART_DIVIDE)) uart (.clk(clk), .rx(uart_rx), .tx(uart_tx), .received(received), .transmit(transmit), .tx_byte(tx_byte), .rx_byte(rx_byte), .is_receiving(is_receiving), .is_transmitting(is_transmitting));
78 `define STATE_PROPAGATE 1
79 `define STATE_EXECUTE 2
82 reg [5:0] state = `STATE_IDLE;
84 assign led[3:0] = led_out;
87 always @ (posedge clk) begin
90 if(uart_ptr == 4) begin
91 last_op <= op_from_uart;
93 state <= `STATE_PROPAGATE;
96 else if (received) begin
97 from_uart[uart_ptr] <= rx_byte;
98 uart_ptr <= uart_ptr + 1;
103 `STATE_PROPAGATE: begin
106 else if(uart_ptr == 4) begin
109 if(last_op == `OP_ROUTE) begin
110 state <= `STATE_ROUTE;
113 state <= `STATE_EXECUTE;
115 end else if(!is_transmitting && ready_in) begin
116 tx_byte <= from_uart[uart_ptr];
118 uart_ptr <= uart_ptr + 1;
122 `STATE_EXECUTE: begin
124 state <= `STATE_IDLE;
130 else if(uart_ptr == 4) begin
132 state <= `STATE_IDLE;
133 end else if(!is_transmitting && ready_in) begin
134 tx_byte <= route_storei[uart_ptr];
136 uart_ptr <= uart_ptr + 1;
142 // wire ready = (state == 0 && !is_receiving);