worker.v

   1 `include "pll.v"
   2 `include "ram.v"
   3 `include "chip.v"
   4 `include "uart.v"
   5
   6 `ifdef SIM
   7  `define UART_DIVIDE 1
   8 `else
   9  `define UART_DIVIDE 1
  10  // s/192/3/ for 19200 baud uart
  11 `endif
  12
  13 module worker (input CLKin, output [4:0] led, output uart_tx, input uart_rx, output reg ready_out = 1, input ready_in);
  14    wire clk;
  15    wire clk_tmp;
  16
  17    //pll pll (.clock_in(CLKin), .clock_out(clk));
  18
  19    reg [20:0] counter = 0;
  20
  21    reg            clk = 0;
  22
  23    always @ (posedge CLKin) begin
  24           if(counter == 5000) begin
  25                  counter <= 0;
  26                  clk <= 1 - clk;
  27           end
  28           else
  29                 counter <= counter + 1;
  30    end
  31
  32    wire [11:0] mem_addr;
  33    wire [63:0] mem_in;
  34    wire [63:0] mem_out;
  35    wire            mem_write;
  36
  37    RAM #(.ADDRESS_BITS(8)) ram (.clk(clk), .write(mem_write), .addr(mem_addr), .in(mem_in), .out(mem_out));
  38
  39    reg [7:0]   from_uart [3:0];
  40    reg [2:0]   uart_ptr = 0;
  41
  42    wire [15:0] I  = {from_uart[1], from_uart[0]};
  43    assign mem_addr = from_uart[2];
  44    wire [2:0]  op_from_uart = from_uart[3][2:0];
  45    wire            CS = from_uart[3][3];
  46
  47    reg [2:0]   op = 0;
  48
  49    reg [2:0]   last_op = 0;
  50
  51    reg [15:0]  I;
  52    reg             CS;
  53
  54    chip chip (.clk(clk), .op(op), .I(I), .io_pin(0), .CS(CS), .mem_in(mem_in), .mem_out(mem_out), .mem_write(mem_write));
  55
  56    wire            received;
  57    wire [7:0]  rx_byte;
  58    reg             transmit = 0;
  59    reg  [7:0]  tx_byte = 0;
  60    wire            is_receiving;
  61    wire            is_transmitting;
  62
  63    // 19200 (actually 300) baud uart
  64    uart #(.CLOCK_DIVIDE(`UART_DIVIDE)) uart (.clk(clk), .rx(uart_rx), .tx(uart_tx), .received(received), .transmit(transmit), .tx_byte(tx_byte), .rx_byte(rx_byte), .is_receiving(is_receiving), .is_transmitting(is_transmitting));
  65
  66    assign led[0] = is_transmitting;
  67    assign led[4] = received;
  68 //   assign led[3:1] = last_op;
  69
  70    assign led[2] = |mem_out; // so that mem_out is used
  71
  72    // 0 is idle
  73 `define STATE_IDLE 0
  74 `define STATE_PROPAGATE 1
  75 `define STATE_EXECUTE 2
  76 `define STATE_ROUTE 3
  77
  78    reg [5:0]   state = 0;
  79
  80 //   assign led[4:2] = state;
  81
  82    always @ (posedge clk) begin
  83           case(state)
  84                 `STATE_IDLE: begin
  85                    if(uart_ptr == 4) begin
  86                           last_op <= op_from_uart;
  87                           uart_ptr <= 0;
  88                           state <= `STATE_PROPAGATE;
  89                           ready_out <= 0;
  90                    end
  91                    else if (received) begin
  92                           from_uart[uart_ptr] <= rx_byte;
  93                           uart_ptr <= uart_ptr + 1;
  94                    end else
  95                          ready_out <= 1;
  96                 end
  97
  98                 `STATE_PROPAGATE: begin
  99                    if(transmit)
 100                           transmit <= 0;
 101                    else if(uart_ptr == 4) begin
 102                           uart_ptr <= 0;
 103                           if(op == `OP_ROUTE) begin
 104                                  state <= `STATE_ROUTE;
 105                           end else begin
 106                                  op <= last_op;
 107                                  state <= `STATE_EXECUTE;
 108                           end
 109                    end else if(!is_transmitting && ready_in) begin
 110                           tx_byte <= from_uart[uart_ptr];
 111                           transmit <= 1;
 112                           uart_ptr <= uart_ptr + 1;
 113                    end
 114                 end
 115
 116                 `STATE_EXECUTE: begin
 117                    op <= 0;
 118                    state <= `STATE_IDLE;
 119                 end
 120
 121                 `STATE_ROUTE: begin
 122                    state <= `STATE_IDLE; // for now
 123                 end
 124           endcase
 125
 126           /*
 127
 128           if (state == 1 && op != `OP_READ) begin
 129                  op <= 0;
 130                  state <= 0;
 131           end
 132
 133           if (state == 1 && op == `OP_READ) begin
 134                  op <= 0;
 135                  state <= 2;
 136                  transmit <= 1;
 137                  tx_byte <= mem_out[7:0];
 138           end
 139
 140           if (state == 2 && transmit) begin
 141                  transmit <= 0;
 142           end
 143
 144           if (state == 2 && !transmit && !is_transmitting) begin
 145                  state <= 3;
 146                  transmit <= 1;
 147                  tx_byte <= mem_out[15:8];
 148           end
 149
 150           if (state == 3) begin
 151                  transmit <= 0;
 152                  state <= 0;
 153           end */
 154    end
 155
 156    wire ready = (state == 0 && !is_receiving);
 157
 158    assign ready_out = ready_in & ready;
 159
 160 endmodule