writer.v

   1 `define STATE_START        3'b000
   2 `define STATE_WRITE1_WAIT  3'b001
   3 `define STATE_WRITE1       3'b010
   4 `define STATE_WRITE2_WAIT  3'b011
   5 `define STATE_WRITE2       3'b100
   6 `define STATE_INCREMENT    3'b101
   7 `define STATE_FINISHED     3'b111
   8
   9 module WRITER (input clk, input clk_enable, output [7:0] tx_byte, output tx_signal, input tx_busy, output finished, output [12:0] ram_addr, input [15:0] ram_do, input [12:0] freeptr);
  10    reg [2:0] state = `STATE_START;
  11    reg [12:0] current_index;
  12
  13    assign ram_addr = current_index;
  14    assign finished = state == `STATE_FINISHED;
  15
  16    always @* begin
  17           case(state)
  18                 `STATE_WRITE1: begin
  19                    tx_signal <= 1;
  20                    tx_byte   <= ram_do[15:8];
  21                 end
  22
  23                 `STATE_WRITE2: begin
  24                    tx_signal <= 1;
  25                    tx_byte   <= ram_do[7:0];
  26                 end
  27
  28                 default: begin
  29                    tx_signal <= 0;
  30                    tx_byte   <= 12'dx;
  31                 end
  32           endcase
  33    end
  34
  35    always @ (posedge clk) begin
  36          if (clk_enable) begin
  37                 case(state)
  38                   `STATE_START: begin
  39                          current_index <= 4;
  40                          state <= `STATE_WRITE1_WAIT;
  41                   end
  42
  43                   `STATE_WRITE1_WAIT: begin
  44                          if(!tx_busy) state <= `STATE_WRITE1;
  45                   end
  46
  47                   `STATE_WRITE1: state <= `STATE_WRITE2_WAIT;
  48
  49                   `STATE_WRITE2_WAIT: begin
  50                          if(!tx_busy) state <= `STATE_WRITE2;
  51                   end
  52
  53                   `STATE_WRITE2: state <= `STATE_INCREMENT;
  54
  55                   `STATE_INCREMENT: begin
  56                          current_index <= current_index + 1;
  57                          if(current_index >= freeptr) begin
  58                                 state <= `STATE_FINISHED;
  59                          end else begin
  60                                 state <= `STATE_WRITE1_WAIT;
  61                          end
  62                   end
  63
  64                   `STATE_FINISHED: state <= `STATE_START;
  65
  66                   default: state <= `STATE_START;
  67                 endcase // case (state)
  68          end // if (clk_enable)
  69    end
  70 endmodule