Several cleanups

[clump.git] / lisp_processor.v

diff --git a/lisp_processor.v b/lisp_processor.v
index c4f737219d4a2fd5cc8f89095e78069161418b91..b22f3f1fd4dd6d0d5400566ee012f2685fe33507 100644 (file)
--- a/lisp_processor.v
+++ b/lisp_processor.v
@@ -21,6 +21,16 @@
 `define GCOP_RDQA     4'd14
 `define GCOP_RDQCDRRX 4'd15
 
+`define STATE_READ  3'b100
+`define STATE_RUN   3'b010
+`define STATE_WRITE 3'b001
+
+`ifdef SIM
+ `define START_STATE `STATE_RUN
+`else
+ `define START_STATE `STATE_READ
+`endif
+
 `ifdef SIM
  `define UART_DIVIDE 1
 `else
@@ -28,18 +38,19 @@
 `endif
 
 module cpu (input clk, output [4:0] led, output uart_tx, input uart_rx);
-   wire [15:0] result;
+   reg [3:0] state = `START_STATE;
 
-   reg [5:0]   initial_reset = 30;
-   always @ (posedge clk)
-        if (initial_reset) initial_reset <= initial_reset - 1;
+   wire         is_reading = state == `STATE_READ;
+   wire         is_running = state == `STATE_RUN;
+   wire         is_writing = state == `STATE_WRITE;
 
-   wire reset = |initial_reset || reader_active || writer_clock_enable;
-   reg [1:0]  counter = 0;
+   wire reset = !is_running;
+   reg         counter = 0;
 
-   wire gc_clock_enable   = counter[0] &  counter[1] & !reset;
-   wire eval_clock_enable = counter[0] & !counter[1] & step_eval & !reset;
-   wire writer_clock_enable = counter[0] & counter[1] & writer_active;
+   wire gc_clock_enable   = is_running;
+   wire eval_clock_enable = step_eval & is_running;
+   wire reader_clock_enable = is_reading;
+   wire writer_clock_enable = is_writing;
 
    always @ (posedge clk)
         counter <= counter + 1;
@@ -65,16 +76,13 @@ module cpu (input clk, output [4:0] led, output uart_tx, input uart_rx);
 
    wire [12:0] writer_ram_addr;
 
-   wire           reader_active;
-
-   wire        ram_we = reader_active ? reader_ram_we : gc_ram_we;
-   wire [12:0] ram_addr = reader_active ? reader_ram_addr : writer_active ? writer_ram_addr : gc_ram_addr;
-   wire [15:0] ram_di = reader_active ? reader_ram_di : gc_ram_di;
+   wire        ram_we = reader_clock_enable ? reader_ram_we : gc_ram_we;
+   wire [12:0] ram_addr = reader_clock_enable ? reader_ram_addr : writer_clock_enable ? writer_ram_addr : gc_ram_addr;
+   wire [15:0] ram_di = reader_clock_enable ? reader_ram_di : gc_ram_di;
    wire [15:0] ram_do;
 
+   wire           reader_finished;
    wire                   writer_finished;
-   reg                    writer_started = 0;
-   reg                    writer_active = 0;
 
    GCRAM gcram (.clk(clk), .we(ram_we), .addr(ram_addr), .di(ram_di), .do(ram_do));
 
@@ -82,7 +90,7 @@ module cpu (input clk, output [4:0] led, output uart_tx, input uart_rx);
 
    EVAL eval (.clk(clk), .rst(reset), .clk_enable(eval_clock_enable), .Ein(E2), .Eout(E1), .gcop(gcop), .ostate(eostate), .conn_ea(conn_ea), .conn_et(conn_et));
 
-   READER reader (.clk(clk), .clk_enable(!initial_reset), .rx_byte(uart_rx_byte), .rx_signal(uart_rx_signal), .active(reader_active), .ram_we(reader_ram_we), .ram_addr(reader_ram_addr), .ram_di(reader_ram_di));
+   READER reader (.clk(clk), .clk_enable(reader_clock_enable), .rx_byte(uart_rx_byte), .rx_signal(uart_rx_signal), .finished(reader_finished), .ram_we(reader_ram_we), .ram_addr(reader_ram_addr), .ram_di(reader_ram_di));
 
    WRITER writer (.clk(clk), .clk_enable(writer_clock_enable), .tx_byte(uart_tx_byte), .tx_signal(uart_tx_signal), .tx_busy(uart_is_transmitting), .finished(writer_finished), .ram_addr(writer_ram_addr), .ram_do(ram_do), .P(P));
 
@@ -98,24 +106,23 @@ module cpu (input clk, output [4:0] led, output uart_tx, input uart_rx);
    wire [7:0] uart_tx_byte;
 
    always @ (posedge clk) begin
-         if(writer_finished)
-               writer_active <= 0;
-
-         if(reader_active) begin
-                writer_started <= 0;
-         end else if(eostate == 5'd7 && !writer_started) begin
-                writer_started <= 1;
-                writer_active <= 1;
-         end
+         if(is_writing & writer_finished)
+               state <= `STATE_READ;
+
+         if(is_reading & reader_finished)
+               state <= `STATE_RUN;
+
+         if(is_running & eostate == 5'd7)
+               state <= `STATE_WRITE;
    end
 
    // 4800 baud uart
    uart #(.CLOCK_DIVIDE(`UART_DIVIDE)) uart (.clk(clk), .rx(uart_rx), .tx(uart_tx), .transmit(uart_tx_signal), .tx_byte(uart_tx_byte), .received(uart_rx_signal), .rx_byte(uart_rx_byte), .is_receiving(uart_is_receiving), .is_transmitting(uart_is_transmitting), .recv_error (uart_rx_error));
 
    // Assign the outputs
-   assign led[0] = eval_clock_enable;
-   assign led[1] = uart_is_transmitting;
-   assign led[2] = uart_is_receiving;
-   assign led[3] = writer_finished;
-   assign led[4] = !reset;
+   assign led[0] = is_reading;
+   assign led[1] = uart_is_receiving;
+   assign led[2] = is_writing;
+   assign led[3] = uart_is_transmitting;
+   assign led[4] = is_running;
 endmodule