`define STATE_READ1 2'd2
`define STATE_READ2 2'd3
-module READER (input clk, input clk_enable, input [7:0] rx_byte, input rx_signal, output reg active, output reg ram_we, output [12:0] ram_addr, output reg [15:0] ram_di);
+module READER (input clk, input clk_enable, input [7:0] rx_byte, input rx_signal, output reg finished = 0, output reg ram_we, output [12:0] ram_addr, output reg [15:0] ram_di);
reg [1:0] state = `STATE_IDLE;
- reg [12:0] words_left = 0;
- reg [12:0] current_index = 0;
+ reg [12:0] words_left;
+ reg [12:0] current_index;
assign ram_addr = current_index;
words_left[12:8] <= rx_byte[4:0];
words_left[7:0] <= 0;
current_index <= -1;
- active <= 1;
state <= `STATE_LENGTH;
- end else
- active <= 0;
+ end
end
`STATE_LENGTH: begin
if(rx_signal) begin
ram_di[7:0] <= rx_byte;
ram_we <= 1;
- state <= |words_left ? `STATE_READ1 : `STATE_IDLE;
+ if(|words_left) begin
+ state <= `STATE_READ1;
+ end else begin
+ state <= `STATE_IDLE;
+ finished <= 1;
+ end
end
end
endcase
- end
+ end // if (clk_enable)
+ else
+ finished <= 0;
endmodule