Add diagrams and pictures

[clump.git] / yosys-sim-script

diff --git a/yosys-sim-script b/yosys-sim-script
index eae3049a4d11e22db9243864abcea405992f8dee..f82bfb456f6efde9e1f09e2f3d34d45b4e070ef6 100755 (executable)
--- a/yosys-sim-script
+++ b/yosys-sim-script
@@ -1,3 +1,3 @@
-read_verilog -sv flash.v
-prep -top top -nordff
-sim -clock CLK -vcd test.vcd -n 200
+read_verilog -sv -DSIM toplevel.v
+prep -top cpu -nordff
+sim -clock clk -vcd test.vcd -n 3000