-`define STATE_START 2'b00
-`define STATE_WRITE1 2'b01
-`define STATE_WRITE2 2'b10
-`define STATE_INCREMENT 2'b11
-
-module WRITER (input clk, input clk_enable, output reg [7:0] tx_byte, output reg tx_signal = 0, input tx_busy, output reg finished = 0, output [12:0] ram_addr, input [15:0] ram_do, input [12:0] freeptr);
- reg [1:0] state = `STATE_START;
+`define STATE_START 3'b000
+`define STATE_WRITE1_WAIT 3'b001
+`define STATE_WRITE1 3'b010
+`define STATE_WRITE2_WAIT 3'b011
+`define STATE_WRITE2 3'b100
+`define STATE_INCREMENT 3'b101
+`define STATE_FINISHED 3'b111