+`define STATE_WRITE_TYPE 3'd0
+`define STATE_WRITE1 3'd1
+`define STATE_WRITE2 3'd2
+`define STATE_WRITE3 3'd3
+`define STATE_WRITE4 3'd4
+
+module WRITER (input clk, input clk_enable, output [7:0] uart_tx_byte, output reg uart_tx_signal = 0, input uart_is_transmitting, output reg finished = 0, input [15:0] result);
+ reg [2:0] state = `STATE_WRITE_TYPE;
+ reg [3:0] tx_hex = 0;
+
+ hex_to_ascii h2a (.hex(tx_hex), .ascii(uart_tx_byte));
+
+ always @ (posedge clk)
+ if (clk_enable) begin
+ if(uart_tx_signal)
+ uart_tx_signal <= 0;
+
+ case(state)
+ `STATE_WRITE_TYPE: begin
+ finished <= 0;
+ if(!uart_is_transmitting && !uart_tx_signal) begin
+ uart_tx_signal <= 1;
+ tx_hex <= {1'b0, result[15:13]};
+ state <= `STATE_WRITE1;
+ end
+ end
+
+ `STATE_WRITE1: begin
+ if(!uart_is_transmitting && !uart_tx_signal) begin
+ uart_tx_signal <= 1;
+ tx_hex <= {3'b0, result[12]};
+ state <= `STATE_WRITE2;
+ end
+ end
+
+ `STATE_WRITE2: begin
+ if(!uart_is_transmitting && !uart_tx_signal) begin
+ uart_tx_signal <= 1;
+ tx_hex <= result[11:8];
+ state <= `STATE_WRITE3;
+ end
+ end
+
+ `STATE_WRITE3: begin
+ if(!uart_is_transmitting && !uart_tx_signal) begin
+ uart_tx_signal <= 1;
+ tx_hex <= result[7:4];
+ state <= `STATE_WRITE4;
+ end
+ end
+
+ `STATE_WRITE4: begin
+ if(!uart_is_transmitting && !uart_tx_signal) begin
+ uart_tx_signal <= 1;
+ tx_hex <= result[3:0];
+ finished <= 1;
+ state <= `STATE_WRITE_TYPE;
+ end
+ end
+ endcase
+ end
+endmodule