1 `include "processor_4.v"
3 module top (input CLK, output [7:0] OUT_C, output [2:0] OUT_R, output [3:0] IN_C, input [3:0] IN_R, output [3:0] IND, output UART_TX, input UART_RX);
7 // Prescaler on the clock
9 reg [24:0] counter = 0;
11 always @ (posedge CLK) begin
13 counter <= counter + 1;
19 reg [3:0] shift_in = 4'b1110;
21 always @ (negedge counter[13]) begin
23 shift_in <= { shift_in[2:0], shift_in[3] };
27 assign IN_C = shift_in;
29 reg [15:0] buttons = 0;
31 always @ (posedge counter[13]) begin
35 buttons[0] <= !IN_R[0];
36 buttons[4] <= !IN_R[1];
37 buttons[8] <= !IN_R[2];
38 buttons[12] <= !IN_R[3];
41 buttons[1] <= !IN_R[0];
42 buttons[5] <= !IN_R[1];
43 buttons[9] <= !IN_R[2];
44 buttons[13] <= !IN_R[3];
47 buttons[2] <= !IN_R[0];
48 buttons[6] <= !IN_R[1];
49 buttons[10] <= !IN_R[2];
50 buttons[14] <= !IN_R[3];
53 buttons[3] <= !IN_R[0];
54 buttons[7] <= !IN_R[1];
55 buttons[11] <= !IN_R[2];
56 buttons[15] <= !IN_R[3];
62 // Connect up the processor
64 PROCESSOR cpu(.clk(CLK),//counter[20]),
71 // Handle output stuff
75 reg [2:0] shift_out = 3'b001;
77 always @ (posedge counter[7]) begin
79 if (shift_out[2] == 1)
81 if (shift_out[0] == 1)
83 if (shift_out[1] == 1)
86 shift_out <= { shift_out[1:0], shift_out[2] };
90 assign OUT_R = shift_out;