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[yule.git] / reader.v
1 `define STATE_IDLE 2'd0
2 `define STATE_LENGTH 2'd1
3 `define STATE_READ1 2'd2
4 `define STATE_READ2 2'd3
5
6 module READER (input clk, input clk_enable, input [7:0] rx_byte, input rx_signal, output reg finished = 0, output reg ram_we, output [12:0] ram_addr, output reg [15:0] ram_di);
7 reg [1:0] state = `STATE_IDLE;
8
9 reg [12:0] words_left;
10 reg [12:0] current_index;
11
12 assign ram_addr = current_index;
13
14 always @ (posedge clk)
15 if (clk_enable) begin
16 if(!rx_signal) ram_we <= 0;
17
18 case(state)
19 `STATE_IDLE: begin
20 if(rx_signal) begin
21 words_left[12:8] <= rx_byte[4:0];
22 words_left[7:0] <= 0;
23 current_index <= -1;
24 state <= `STATE_LENGTH;
25 end
26 end
27
28 `STATE_LENGTH: begin
29 if(rx_signal) begin
30 words_left[7:0] <= rx_byte;
31 state <= `STATE_READ1;
32 end
33 end
34
35 `STATE_READ1: begin
36 if(rx_signal) begin
37 ram_di[15:8] <= rx_byte;
38 current_index <= current_index + 1;
39 words_left <= words_left - 1;
40 state <= `STATE_READ2;
41 end
42 end
43
44 `STATE_READ2: begin
45 if(rx_signal) begin
46 ram_di[7:0] <= rx_byte;
47 ram_we <= 1;
48 if(|words_left) begin
49 state <= `STATE_READ1;
50 end else begin
51 state <= `STATE_IDLE;
52 finished <= 1;
53 end
54 end
55 end
56 endcase
57 end // if (clk_enable)
58 else
59 finished <= 0;
60 endmodule
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