writer.v

   1 `define STATE_WRITE_TYPE 3'd0
   2 `define STATE_WRITE1     3'd1
   3 `define STATE_WRITE2     3'd2
   4 `define STATE_WRITE3     3'd3
   5 `define STATE_WRITE4     3'd4
   6
   7 module WRITER (input clk, input clk_enable, output [7:0] uart_tx_byte, output reg uart_tx_signal = 0, input uart_is_transmitting, output reg finished = 0, input [15:0] result);
   8    reg [2:0] state = `STATE_WRITE_TYPE;
   9    reg [3:0] tx_hex = 0;
  10
  11    hex_to_ascii h2a (.hex(tx_hex), .ascii(uart_tx_byte));
  12
  13    always @ (posedge clk)
  14          if (clk_enable) begin
  15                 if(uart_tx_signal)
  16                   uart_tx_signal <= 0;
  17
  18                 case(state)
  19                   `STATE_WRITE_TYPE: begin
  20                          finished <= 0;
  21                          if(!uart_is_transmitting && !uart_tx_signal) begin
  22                                 uart_tx_signal <= 1;
  23                                 tx_hex <= {1'b0, result[15:13]};
  24                                 state <= `STATE_WRITE1;
  25                          end
  26                   end
  27
  28                   `STATE_WRITE1: begin
  29                          if(!uart_is_transmitting && !uart_tx_signal) begin
  30                                 uart_tx_signal <= 1;
  31                                 tx_hex <= {3'b0, result[12]};
  32                                 state <= `STATE_WRITE2;
  33                          end
  34                   end
  35
  36                   `STATE_WRITE2: begin
  37                          if(!uart_is_transmitting && !uart_tx_signal) begin
  38                                 uart_tx_signal <= 1;
  39                                 tx_hex <= result[11:8];
  40                                 state <= `STATE_WRITE3;
  41                          end
  42                   end
  43
  44                   `STATE_WRITE3: begin
  45                          if(!uart_is_transmitting && !uart_tx_signal) begin
  46                                 uart_tx_signal <= 1;
  47                                 tx_hex <= result[7:4];
  48                                 state <= `STATE_WRITE4;
  49                          end
  50                   end
  51
  52                   `STATE_WRITE4: begin
  53                          if(!uart_is_transmitting && !uart_tx_signal) begin
  54                                 uart_tx_signal <= 1;
  55                                 tx_hex <= result[3:0];
  56                                 finished <= 1;
  57                                 state <= `STATE_WRITE_TYPE;
  58                          end
  59                   end
  60                 endcase
  61          end
  62 endmodule