]> iEval git - yule.git/blob - yosys-sim-script
projects / yule.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Make words 16 bits wide
[yule.git] / yosys-sim-script
1 read_verilog -sv flash.v
2 prep -top top -nordff
3 sim -clock CLK -vcd test.vcd -n 1000
Yet Unfinished Lisp Evaluator
This page took 0.031469 seconds and 4 git commands to generate.