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9cffede952a7db8d46e6e4a9b1e7a326590ea9ec
[yule.git]
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yosys-sim-script
1
read_verilog -sv -DSIM flash.v
2
prep -top top -nordff
3
sim -clock CLK -vcd test.vcd -n 3000
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projects / yule.git / blob