]> iEval git - yule.git/blob - yosys-sim-script
eae3049a4d11e22db9243864abcea405992f8dee
[yule.git] / yosys-sim-script
1 read_verilog -sv flash.v
2 prep -top top -nordff
3 sim -clock CLK -vcd test.vcd -n 200
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