Proper macros for simulation/normal running

[yule.git] / yosys-sim-script

diff --git a/yosys-sim-script b/yosys-sim-script
index 965efd1672ab2382a21d9c02d073ea487a6adeb7..9cffede952a7db8d46e6e4a9b1e7a326590ea9ec 100755 (executable)
--- a/yosys-sim-script
+++ b/yosys-sim-script
@@ -1,3 +1,3 @@
-read_verilog -sv flash.v
+read_verilog -sv -DSIM flash.v
 prep -top top -nordff
-sim -clock CLK -vcd test.vcd -n 1000
+sim -clock CLK -vcd test.vcd -n 3000