Add controller module

diff --git a/controller.v b/controller.v
new file mode 100644 (file)
index 0000000..1fb20c0
--- /dev/null
+++ b/controller.v
@@ -0,0 +1,44 @@
+`define STATE_READ  3'b100
+`define STATE_RUN   3'b010
+`define STATE_WRITE 3'b001
+
+`ifdef SIM
+ `define START_STATE `STATE_RUN
+`else
+ `define START_STATE `STATE_READ
+`endif
+
+module CTRL (input clk, input step_eval, input reader_finished, input eval_finished, input writer_finished, output gc_clock_enable, output eval_clock_enable, output reader_clock_enable, output writer_clock_enable, output reset, input gc_ram_we, input reader_ram_we, input [12:0] gc_ram_addr, input [12:0] reader_ram_addr, input [12:0] writer_ram_addr, input [15:0] gc_ram_di, input [15:0] reader_ram_di, output ram_we, output [12:0] ram_addr, output [15:0] ram_di, input uart_is_receiving, input uart_is_transmitting, output [4:0] led);
+   reg [3:0] state = `START_STATE;
+
+   wire         is_reading = state == `STATE_READ;
+   wire         is_running = state == `STATE_RUN;
+   wire         is_writing = state == `STATE_WRITE;
+
+   assign gc_clock_enable   = is_running;
+   assign eval_clock_enable = step_eval & is_running;
+   assign reader_clock_enable = is_reading;
+   assign writer_clock_enable = is_writing;
+   assign reset = !is_running;
+
+   always @ (posedge clk) begin
+         if(is_writing & writer_finished)
+               state <= `STATE_READ;
+
+         if(is_reading & reader_finished)
+               state <= `STATE_RUN;
+
+         if(is_running & eval_finished)
+               state <= `STATE_WRITE;
+   end
+
+   assign ram_we = reader_clock_enable ? reader_ram_we : gc_ram_we;
+   assign ram_addr = reader_clock_enable ? reader_ram_addr : writer_clock_enable ? writer_ram_addr : gc_ram_addr;
+   assign ram_di = reader_clock_enable ? reader_ram_di : gc_ram_di;
+
+   assign led[0] = is_reading;
+   assign led[1] = uart_is_receiving;
+   assign led[2] = is_writing;
+   assign led[3] = uart_is_transmitting;
+   assign led[4] = is_running;
+endmodule

diff --git a/eval.v b/eval.v
index 96cb68e2c8e865bf1da65449121c60a60495a775..5bf806bd3fbe2ba72233ca98d5215796ffd4c77c 100644 (file)
--- a/eval.v
+++ b/eval.v
@@ -1,5 +1,5 @@
-module EVAL(input clk, input clk_enable, input rst, input [15:0] Ein, output [15:0] Eout, output [3:0] gcop, output [5:0] ostate, input conn_ea, input conn_et);
-   reg [21:0] rom_output;
+module EVAL(input clk, input clk_enable, input rst, input [15:0] Ein, output [15:0] Eout, output [3:0] gcop, output [5:0] ostate, output eval_finished, input conn_ea, input conn_et);
+   reg [22:0] rom_output;
    reg [5:0]  eostate;
    reg [5:0]  enstate;
 
@@ -7,6 +7,7 @@ module EVAL(input clk, input clk_enable, input rst, input [15:0] Ein, output [15
    initial eostate <= 0;
 `endif
 
+   assign eval_finished = rom_output[22];
    wire et_lit = rom_output[21];
    wire ea_lit = rom_output[20];
    wire eaz_etz_eqv_disp = rom_output[19];
@@ -30,65 +31,65 @@ module EVAL(input clk, input clk_enable, input rst, input [15:0] Ein, output [15
 
    always @* begin
          case(eostate)
-               6'o00:   begin rom_output <= 22'o14004002; enstate <= 6'o01; end
-               6'o01:   begin rom_output <= 22'o14001000; enstate <= 6'o33; end
-               6'o02:   begin rom_output <= 22'o02040200; enstate <= 6'o23; end
-               6'o03:   begin rom_output <= 22'o00400120; enstate <= 6'o20; end
-               6'o04:   begin rom_output <= 22'o00010110; enstate <= 6'o64; end
-               6'o05:   begin rom_output <= 22'o00001170; enstate <= 6'o22; end
-               6'o06:   begin rom_output <= 22'o14000013; enstate <= 6'o71; end
-               6'o07:   begin rom_output <= 22'o00000000; enstate <= 6'o07; end
-               6'o10:   begin rom_output <= 22'o00020200; enstate <= 6'o45; end
-               6'o11:   begin rom_output <= 22'o00020200; enstate <= 6'o45; end
-               6'o12:   begin rom_output <= 22'o00100140; enstate <= 6'o02; end
-               6'o13:   begin rom_output <= 22'o00020200; enstate <= 6'o45; end
-               6'o14:   begin rom_output <= 22'o00020010; enstate <= 6'o53; end
-               6'o15:   begin rom_output <= 22'o00020010; enstate <= 6'o03; end
-               6'o16:   begin rom_output <= 22'o14002000; enstate <= 6'o40; end
-               6'o17:   begin rom_output <= 22'o00020010; enstate <= 6'o30; end
-               6'o20:   begin rom_output <= 22'o00100110; enstate <= 6'o21; end
-               6'o21:   begin rom_output <= 22'o10004161; enstate <= 6'o61; end
-               6'o22:   begin rom_output <= 22'o00004030; enstate <= 6'o24; end
-               6'o23:   begin rom_output <= 22'o00010500; enstate <= 6'o02; end
-               6'o24:   begin rom_output <= 22'o02010070; enstate <= 6'o33; end
-               6'o25:   begin rom_output <= 22'o00000040; enstate <= 6'o26; end
-               6'o26:   begin rom_output <= 22'o00010120; enstate <= 6'o30; end
-               6'o27:   begin rom_output <= 22'o00000240; enstate <= 6'o45; end
-               6'o30:   begin rom_output <= 22'o00000350; enstate <= 6'o45; end
-               6'o31:   begin rom_output <= 22'o00001150; enstate <= 6'o32; end
-               6'o32:   begin rom_output <= 22'o02200010; enstate <= 6'o63; end
-               6'o33:   begin rom_output <= 22'o01000440; enstate <= 6'o10; end
-               6'o34:   begin rom_output <= 22'o00201000; enstate <= 6'o35; end
-               6'o35:   begin rom_output <= 22'o00010020; enstate <= 6'o62; end
-               6'o36:   begin rom_output <= 22'o00400120; enstate <= 6'o54; end
-               6'o37:   begin rom_output <= 22'o01000430; enstate <= 6'o10; end
-               6'o40:   begin rom_output <= 22'o00020010; enstate <= 6'o36; end
-               6'o41:   begin rom_output <= 22'o00010020; enstate <= 6'o30; end
-               6'o42:   begin rom_output <= 22'o00010010; enstate <= 6'o30; end
-               6'o43:   begin rom_output <= 22'o00200010; enstate <= 6'o25; end
-               6'o44:   begin rom_output <= 22'o02010000; enstate <= 6'o55; end
-               6'o45:   begin rom_output <= 22'o01400020; enstate <= 6'o04; end
-               6'o46:   begin rom_output <= 22'o00200200; enstate <= 6'o45; end
-               6'o47:   begin rom_output <= 22'o00010010; enstate <= 6'o31; end
-               6'o50:   begin rom_output <= 22'o00000060; enstate <= 6'o51; end
-               6'o51:   begin rom_output <= 22'o00004030; enstate <= 6'o52; end
-               6'o52:   begin rom_output <= 22'o01000450; enstate <= 6'o40; end
-               6'o53:   begin rom_output <= 22'o00100120; enstate <= 6'o70; end
-               6'o54:   begin rom_output <= 22'o00100110; enstate <= 6'o56; end
-               6'o55:   begin rom_output <= 22'o14000201; enstate <= 6'o45; end
-               6'o56:   begin rom_output <= 22'o00200110; enstate <= 6'o60; end
-               6'o57:   begin rom_output <= 22'o14000200; enstate <= 6'o45; end
-               6'o60:   begin rom_output <= 22'o10004160; enstate <= 6'o61; end
-               6'o61:   begin rom_output <= 22'o00020020; enstate <= 6'o62; end
-               6'o62:   begin rom_output <= 22'o01000550; enstate <= 6'o10; end
-               6'o63:   begin rom_output <= 22'o02000030; enstate <= 6'o63; end
-               6'o64:   begin rom_output <= 22'o00002150; enstate <= 6'o65; end
-               6'o65:   begin rom_output <= 22'o00400010; enstate <= 6'o66; end
-               6'o66:   begin rom_output <= 22'o00001040; enstate <= 6'o50; end
-               6'o67:   begin rom_output <= 22'o00100130; enstate <= 6'o34; end
-               6'o70:   begin rom_output <= 22'o10000363; enstate <= 6'o45; end
-               6'o71:   begin rom_output <= 22'o00010130; enstate <= 6'o07; end
-               default: begin rom_output <= 22'o00000000; enstate <= 6'o07; end
+               6'o00:   begin rom_output <= 23'o14004002; enstate <= 6'o01; end
+               6'o01:   begin rom_output <= 23'o14001000; enstate <= 6'o33; end
+               6'o02:   begin rom_output <= 23'o02040200; enstate <= 6'o23; end
+               6'o03:   begin rom_output <= 23'o00400120; enstate <= 6'o20; end
+               6'o04:   begin rom_output <= 23'o00010110; enstate <= 6'o64; end
+               6'o05:   begin rom_output <= 23'o00001170; enstate <= 6'o22; end
+               6'o06:   begin rom_output <= 23'o14000013; enstate <= 6'o71; end
+               6'o07:   begin rom_output <= 23'o00000000 | (1 << 22); enstate <= 6'o07; end
+               6'o10:   begin rom_output <= 23'o00020200; enstate <= 6'o45; end
+               6'o11:   begin rom_output <= 23'o00020200; enstate <= 6'o45; end
+               6'o12:   begin rom_output <= 23'o00100140; enstate <= 6'o02; end
+               6'o13:   begin rom_output <= 23'o00020200; enstate <= 6'o45; end
+               6'o14:   begin rom_output <= 23'o00020010; enstate <= 6'o53; end
+               6'o15:   begin rom_output <= 23'o00020010; enstate <= 6'o03; end
+               6'o16:   begin rom_output <= 23'o14002000; enstate <= 6'o40; end
+               6'o17:   begin rom_output <= 23'o00020010; enstate <= 6'o30; end
+               6'o20:   begin rom_output <= 23'o00100110; enstate <= 6'o21; end
+               6'o21:   begin rom_output <= 23'o10004161; enstate <= 6'o61; end
+               6'o22:   begin rom_output <= 23'o00004030; enstate <= 6'o24; end
+               6'o23:   begin rom_output <= 23'o00010500; enstate <= 6'o02; end
+               6'o24:   begin rom_output <= 23'o02010070; enstate <= 6'o33; end
+               6'o25:   begin rom_output <= 23'o00000040; enstate <= 6'o26; end
+               6'o26:   begin rom_output <= 23'o00010120; enstate <= 6'o30; end
+               6'o27:   begin rom_output <= 23'o00000240; enstate <= 6'o45; end
+               6'o30:   begin rom_output <= 23'o00000350; enstate <= 6'o45; end
+               6'o31:   begin rom_output <= 23'o00001150; enstate <= 6'o32; end
+               6'o32:   begin rom_output <= 23'o02200010; enstate <= 6'o63; end
+               6'o33:   begin rom_output <= 23'o01000440; enstate <= 6'o10; end
+               6'o34:   begin rom_output <= 23'o00201000; enstate <= 6'o35; end
+               6'o35:   begin rom_output <= 23'o00010020; enstate <= 6'o62; end
+               6'o36:   begin rom_output <= 23'o00400120; enstate <= 6'o54; end
+               6'o37:   begin rom_output <= 23'o01000430; enstate <= 6'o10; end
+               6'o40:   begin rom_output <= 23'o00020010; enstate <= 6'o36; end
+               6'o41:   begin rom_output <= 23'o00010020; enstate <= 6'o30; end
+               6'o42:   begin rom_output <= 23'o00010010; enstate <= 6'o30; end
+               6'o43:   begin rom_output <= 23'o00200010; enstate <= 6'o25; end
+               6'o44:   begin rom_output <= 23'o02010000; enstate <= 6'o55; end
+               6'o45:   begin rom_output <= 23'o01400020; enstate <= 6'o04; end
+               6'o46:   begin rom_output <= 23'o00200200; enstate <= 6'o45; end
+               6'o47:   begin rom_output <= 23'o00010010; enstate <= 6'o31; end
+               6'o50:   begin rom_output <= 23'o00000060; enstate <= 6'o51; end
+               6'o51:   begin rom_output <= 23'o00004030; enstate <= 6'o52; end
+               6'o52:   begin rom_output <= 23'o01000450; enstate <= 6'o40; end
+               6'o53:   begin rom_output <= 23'o00100120; enstate <= 6'o70; end
+               6'o54:   begin rom_output <= 23'o00100110; enstate <= 6'o56; end
+               6'o55:   begin rom_output <= 23'o14000201; enstate <= 6'o45; end
+               6'o56:   begin rom_output <= 23'o00200110; enstate <= 6'o60; end
+               6'o57:   begin rom_output <= 23'o14000200; enstate <= 6'o45; end
+               6'o60:   begin rom_output <= 23'o10004160; enstate <= 6'o61; end
+               6'o61:   begin rom_output <= 23'o00020020; enstate <= 6'o62; end
+               6'o62:   begin rom_output <= 23'o01000550; enstate <= 6'o10; end
+               6'o63:   begin rom_output <= 23'o02000030; enstate <= 6'o63; end
+               6'o64:   begin rom_output <= 23'o00002150; enstate <= 6'o65; end
+               6'o65:   begin rom_output <= 23'o00400010; enstate <= 6'o66; end
+               6'o66:   begin rom_output <= 23'o00001040; enstate <= 6'o50; end
+               6'o67:   begin rom_output <= 23'o00100130; enstate <= 6'o34; end
+               6'o70:   begin rom_output <= 23'o10000363; enstate <= 6'o45; end
+               6'o71:   begin rom_output <= 23'o00010130; enstate <= 6'o07; end
+               default: begin rom_output <= 23'o00000000; enstate <= 6'o07; end
          endcase
    end // always @ *
 

diff --git a/lisp_processor.v b/lisp_processor.v
index b22f3f1fd4dd6d0d5400566ee012f2685fe33507..a3b1966d8bc7949336560eef04c53a7c639535eb 100644 (file)
--- a/lisp_processor.v
+++ b/lisp_processor.v
@@ -3,6 +3,7 @@
 `include "reader.v"
 `include "uart.v"
 `include "writer.v"
+`include "controller.v"
 
 `define GCOP_NOP      4'd0
 `define GCOP_CDR      4'd1
@@ -21,16 +22,6 @@
 `define GCOP_RDQA     4'd14
 `define GCOP_RDQCDRRX 4'd15
 
-`define STATE_READ  3'b100
-`define STATE_RUN   3'b010
-`define STATE_WRITE 3'b001
-
-`ifdef SIM
- `define START_STATE `STATE_RUN
-`else
- `define START_STATE `STATE_READ
-`endif
-
 `ifdef SIM
  `define UART_DIVIDE 1
 `else
@@ -38,23 +29,6 @@
 `endif
 
 module cpu (input clk, output [4:0] led, output uart_tx, input uart_rx);
-   reg [3:0] state = `START_STATE;
-
-   wire         is_reading = state == `STATE_READ;
-   wire         is_running = state == `STATE_RUN;
-   wire         is_writing = state == `STATE_WRITE;
-
-   wire reset = !is_running;
-   reg         counter = 0;
-
-   wire gc_clock_enable   = is_running;
-   wire eval_clock_enable = step_eval & is_running;
-   wire reader_clock_enable = is_reading;
-   wire writer_clock_enable = is_writing;
-
-   always @ (posedge clk)
-        counter <= counter + 1;
-
    wire [12:0] P;
    wire [15:0] E1;
    wire [15:0] E2;
@@ -76,19 +50,28 @@ module cpu (input clk, output [4:0] led, output uart_tx, input uart_rx);
 
    wire [12:0] writer_ram_addr;
 
-   wire        ram_we = reader_clock_enable ? reader_ram_we : gc_ram_we;
-   wire [12:0] ram_addr = reader_clock_enable ? reader_ram_addr : writer_clock_enable ? writer_ram_addr : gc_ram_addr;
-   wire [15:0] ram_di = reader_clock_enable ? reader_ram_di : gc_ram_di;
+   wire        ram_we;
+   wire [12:0] ram_addr;
+   wire [15:0] ram_di;
    wire [15:0] ram_do;
 
+   wire           eval_finished;
    wire           reader_finished;
    wire                   writer_finished;
 
+   wire           gc_clock_enable;
+   wire           eval_clock_enable;
+   wire           reader_clock_enable;
+   wire           writer_clock_enable;
+   wire           reset;
+
+   CTRL ctrl (.clk(clk), .step_eval(step_eval), .reader_finished(reader_finished), .eval_finished(eval_finished), .writer_finished(writer_finished), .gc_clock_enable(gc_clock_enable), .eval_clock_enable(eval_clock_enable), .reader_clock_enable(reader_clock_enable), .writer_clock_enable(writer_clock_enable), .reset(reset), .gc_ram_we(gc_ram_we), .reader_ram_we(reader_ram_we), .gc_ram_addr(gc_ram_addr), .reader_ram_addr(reader_ram_addr), .writer_ram_addr(writer_ram_addr), .gc_ram_di(gc_ram_di), .reader_ram_di(reader_ram_di), .ram_we(ram_we), .ram_addr(ram_addr), .ram_di(ram_di), .uart_is_receiving(uart_is_receiving), .uart_is_transmitting(uart_is_transmitting), .led(led));
+
    GCRAM gcram (.clk(clk), .we(ram_we), .addr(ram_addr), .di(ram_di), .do(ram_do));
 
    GC gc (.clk(clk), .rst(reset), .clk_enable(gc_clock_enable), .Ein(E1), .Eout(E2), .gcop(gcop), .ostate(gostate), .step_eval(step_eval), .conn_ea(conn_ea), .conn_et(conn_et), .ram_we(gc_ram_we), .ram_addr(gc_ram_addr), .ram_di(gc_ram_di), .ram_do(ram_do), .Pout(P));
 
-   EVAL eval (.clk(clk), .rst(reset), .clk_enable(eval_clock_enable), .Ein(E2), .Eout(E1), .gcop(gcop), .ostate(eostate), .conn_ea(conn_ea), .conn_et(conn_et));
+   EVAL eval (.clk(clk), .rst(reset), .clk_enable(eval_clock_enable), .Ein(E2), .Eout(E1), .gcop(gcop), .ostate(eostate), .conn_ea(conn_ea), .conn_et(conn_et), .eval_finished(eval_finished));
 
    READER reader (.clk(clk), .clk_enable(reader_clock_enable), .rx_byte(uart_rx_byte), .rx_signal(uart_rx_signal), .finished(reader_finished), .ram_we(reader_ram_we), .ram_addr(reader_ram_addr), .ram_di(reader_ram_di));
 
@@ -105,24 +88,6 @@ module cpu (input clk, output [4:0] led, output uart_tx, input uart_rx);
    wire          uart_tx_signal;
    wire [7:0] uart_tx_byte;
 
-   always @ (posedge clk) begin
-         if(is_writing & writer_finished)
-               state <= `STATE_READ;
-
-         if(is_reading & reader_finished)
-               state <= `STATE_RUN;
-
-         if(is_running & eostate == 5'd7)
-               state <= `STATE_WRITE;
-   end
-
    // 4800 baud uart
    uart #(.CLOCK_DIVIDE(`UART_DIVIDE)) uart (.clk(clk), .rx(uart_rx), .tx(uart_tx), .transmit(uart_tx_signal), .tx_byte(uart_tx_byte), .received(uart_rx_signal), .rx_byte(uart_rx_byte), .is_receiving(uart_is_receiving), .is_transmitting(uart_is_transmitting), .recv_error (uart_rx_error));
-
-   // Assign the outputs
-   assign led[0] = is_reading;
-   assign led[1] = uart_is_receiving;
-   assign led[2] = is_writing;
-   assign led[3] = uart_is_transmitting;
-   assign led[4] = is_running;
 endmodule