Several cleanups

diff --git a/eval.v b/eval.v
index 355a9ffef22379193b675d792e143f071c0a4200..96cb68e2c8e865bf1da65449121c60a60495a775 100644 (file)
--- a/eval.v
+++ b/eval.v
@@ -2,13 +2,10 @@ module EVAL(input clk, input clk_enable, input rst, input [15:0] Ein, output [15
    reg [21:0] rom_output;
    reg [5:0]  eostate;
    reg [5:0]  enstate;
-   reg [15:0]  Ein_latched;
 
-   always @(posedge clk) begin
-         if(clk_enable) begin
-                Ein_latched <= Ein;
-         end
-   end
+`ifdef SIM
+   initial eostate <= 0;
+`endif
 
    wire et_lit = rom_output[21];
    wire ea_lit = rom_output[20];

diff --git a/gc.v b/gc.v
index 2f94a21edec9c85a3d6f7d1b31c5a365553390d3..302041210a72a8c786d3c7149df229a70c741093 100644 (file)
--- a/gc.v
+++ b/gc.v
@@ -4,14 +4,12 @@ module GC (input clk, input clk_enable, input rst, input [15:0] Ein, output [15:
    reg [15:0] rom_output;
    reg [5:0]  gostate;
    reg [5:0]  gnstate;
-   reg [15:0] Ein_latched;
 
-   always @(posedge clk) begin
-         if(rst)
-               Ein_latched <= 16'b0100000000000100; // initial value of E
-         else if(clk_enable)
-               Ein_latched <= Ein;
+`ifdef SIM
+   initial begin
+         gostate <= 0;
    end
+`endif
 
    wire ga_zero_disp = rom_output[15];
    wire gcop_disp    = rom_output[14];
@@ -117,8 +115,8 @@ module GC (input clk, input clk_enable, input rst, input [15:0] Ein, output [15:
    wire [15:0] GfromP = rdP ? {3'b0, P} : 0;
    wire [15:0] GfromP_plus = rdP_plus ? {3'b0, P + 1} : 0;
    wire [15:0] GfromI = conn_i ? ram_do : 0;
-   wire [12:0] GAfromE = conn_ea ? Ein_latched[12:0] : 0;
-   wire [2:0] GTfromE = conn_et ? Ein_latched[15:13] : 0;
+   wire [12:0] GAfromE = conn_ea ? Ein[12:0] : 0;
+   wire [2:0] GTfromE = conn_et ? Ein[15:13] : 0;
    wire [15:0] GfromE = {GTfromE, GAfromE};
 
    assign G = GfromR | GfromQ | GfromP | GfromP_plus | GfromI | GfromE;

diff --git a/gcram.v b/gcram.v
index 0f0c701ae8636268ae44c07ee033a609fb76d3ce..320f99e1022eedbe944c6e4a2a05bdd1b848d020 100644 (file)
--- a/gcram.v
+++ b/gcram.v
@@ -2,10 +2,10 @@ module GCRAM
 (input clk, input we, input[12:0] addr, input[15:0] di, output reg [15:0] do);
    reg [15:0] mem [4095:0];
 
-   always @ (posedge clk)
+   always @ (negedge clk)
         do <= #1 mem[addr];
 
-   always @ (posedge clk)
+   always @ (negedge clk)
         if (we)
           mem[addr] <= #1 di;
 

diff --git a/lisp_processor.v b/lisp_processor.v
index c4f737219d4a2fd5cc8f89095e78069161418b91..b22f3f1fd4dd6d0d5400566ee012f2685fe33507 100644 (file)
--- a/lisp_processor.v
+++ b/lisp_processor.v
@@ -21,6 +21,16 @@
 `define GCOP_RDQA     4'd14
 `define GCOP_RDQCDRRX 4'd15
 
+`define STATE_READ  3'b100
+`define STATE_RUN   3'b010
+`define STATE_WRITE 3'b001
+
+`ifdef SIM
+ `define START_STATE `STATE_RUN
+`else
+ `define START_STATE `STATE_READ
+`endif
+
 `ifdef SIM
  `define UART_DIVIDE 1
 `else
@@ -28,18 +38,19 @@
 `endif
 
 module cpu (input clk, output [4:0] led, output uart_tx, input uart_rx);
-   wire [15:0] result;
+   reg [3:0] state = `START_STATE;
 
-   reg [5:0]   initial_reset = 30;
-   always @ (posedge clk)
-        if (initial_reset) initial_reset <= initial_reset - 1;
+   wire         is_reading = state == `STATE_READ;
+   wire         is_running = state == `STATE_RUN;
+   wire         is_writing = state == `STATE_WRITE;
 
-   wire reset = |initial_reset || reader_active || writer_clock_enable;
-   reg [1:0]  counter = 0;
+   wire reset = !is_running;
+   reg         counter = 0;
 
-   wire gc_clock_enable   = counter[0] &  counter[1] & !reset;
-   wire eval_clock_enable = counter[0] & !counter[1] & step_eval & !reset;
-   wire writer_clock_enable = counter[0] & counter[1] & writer_active;
+   wire gc_clock_enable   = is_running;
+   wire eval_clock_enable = step_eval & is_running;
+   wire reader_clock_enable = is_reading;
+   wire writer_clock_enable = is_writing;
 
    always @ (posedge clk)
         counter <= counter + 1;
@@ -65,16 +76,13 @@ module cpu (input clk, output [4:0] led, output uart_tx, input uart_rx);
 
    wire [12:0] writer_ram_addr;
 
-   wire           reader_active;
-
-   wire        ram_we = reader_active ? reader_ram_we : gc_ram_we;
-   wire [12:0] ram_addr = reader_active ? reader_ram_addr : writer_active ? writer_ram_addr : gc_ram_addr;
-   wire [15:0] ram_di = reader_active ? reader_ram_di : gc_ram_di;
+   wire        ram_we = reader_clock_enable ? reader_ram_we : gc_ram_we;
+   wire [12:0] ram_addr = reader_clock_enable ? reader_ram_addr : writer_clock_enable ? writer_ram_addr : gc_ram_addr;
+   wire [15:0] ram_di = reader_clock_enable ? reader_ram_di : gc_ram_di;
    wire [15:0] ram_do;
 
+   wire           reader_finished;
    wire                   writer_finished;
-   reg                    writer_started = 0;
-   reg                    writer_active = 0;
 
    GCRAM gcram (.clk(clk), .we(ram_we), .addr(ram_addr), .di(ram_di), .do(ram_do));
 
@@ -82,7 +90,7 @@ module cpu (input clk, output [4:0] led, output uart_tx, input uart_rx);
 
    EVAL eval (.clk(clk), .rst(reset), .clk_enable(eval_clock_enable), .Ein(E2), .Eout(E1), .gcop(gcop), .ostate(eostate), .conn_ea(conn_ea), .conn_et(conn_et));
 
-   READER reader (.clk(clk), .clk_enable(!initial_reset), .rx_byte(uart_rx_byte), .rx_signal(uart_rx_signal), .active(reader_active), .ram_we(reader_ram_we), .ram_addr(reader_ram_addr), .ram_di(reader_ram_di));
+   READER reader (.clk(clk), .clk_enable(reader_clock_enable), .rx_byte(uart_rx_byte), .rx_signal(uart_rx_signal), .finished(reader_finished), .ram_we(reader_ram_we), .ram_addr(reader_ram_addr), .ram_di(reader_ram_di));
 
    WRITER writer (.clk(clk), .clk_enable(writer_clock_enable), .tx_byte(uart_tx_byte), .tx_signal(uart_tx_signal), .tx_busy(uart_is_transmitting), .finished(writer_finished), .ram_addr(writer_ram_addr), .ram_do(ram_do), .P(P));
 
@@ -98,24 +106,23 @@ module cpu (input clk, output [4:0] led, output uart_tx, input uart_rx);
    wire [7:0] uart_tx_byte;
 
    always @ (posedge clk) begin
-         if(writer_finished)
-               writer_active <= 0;
-
-         if(reader_active) begin
-                writer_started <= 0;
-         end else if(eostate == 5'd7 && !writer_started) begin
-                writer_started <= 1;
-                writer_active <= 1;
-         end
+         if(is_writing & writer_finished)
+               state <= `STATE_READ;
+
+         if(is_reading & reader_finished)
+               state <= `STATE_RUN;
+
+         if(is_running & eostate == 5'd7)
+               state <= `STATE_WRITE;
    end
 
    // 4800 baud uart
    uart #(.CLOCK_DIVIDE(`UART_DIVIDE)) uart (.clk(clk), .rx(uart_rx), .tx(uart_tx), .transmit(uart_tx_signal), .tx_byte(uart_tx_byte), .received(uart_rx_signal), .rx_byte(uart_rx_byte), .is_receiving(uart_is_receiving), .is_transmitting(uart_is_transmitting), .recv_error (uart_rx_error));
 
    // Assign the outputs
-   assign led[0] = eval_clock_enable;
-   assign led[1] = uart_is_transmitting;
-   assign led[2] = uart_is_receiving;
-   assign led[3] = writer_finished;
-   assign led[4] = !reset;
+   assign led[0] = is_reading;
+   assign led[1] = uart_is_receiving;
+   assign led[2] = is_writing;
+   assign led[3] = uart_is_transmitting;
+   assign led[4] = is_running;
 endmodule

diff --git a/reader.v b/reader.v
index afe85960f62ff25eed516ef66c49dde4735a7566..88e52e71bcf730f7c8a6652304585a64b20271ae 100644 (file)
--- a/reader.v
+++ b/reader.v
@@ -3,11 +3,11 @@
 `define STATE_READ1   2'd2
 `define STATE_READ2   2'd3
 
-module READER (input clk, input clk_enable, input [7:0] rx_byte, input rx_signal, output reg active, output reg ram_we, output [12:0] ram_addr, output reg [15:0] ram_di);
+module READER (input clk, input clk_enable, input [7:0] rx_byte, input rx_signal, output reg finished = 0, output reg ram_we, output [12:0] ram_addr, output reg [15:0] ram_di);
    reg [1:0] state = `STATE_IDLE;
 
-   reg [12:0] words_left = 0;
-   reg [12:0] current_index = 0;
+   reg [12:0] words_left;
+   reg [12:0] current_index;
 
    assign ram_addr = current_index;
 
@@ -21,10 +21,8 @@ module READER (input clk, input clk_enable, input [7:0] rx_byte, input rx_signal
                                words_left[12:8] <= rx_byte[4:0];
                                words_left[7:0] <= 0;
                                current_index <= -1;
-                               active <= 1;
                                state <= `STATE_LENGTH;
-                        end else
-                          active <= 0;
+                        end
                  end
 
                  `STATE_LENGTH: begin
@@ -47,9 +45,16 @@ module READER (input clk, input clk_enable, input [7:0] rx_byte, input rx_signal
                         if(rx_signal) begin
                                ram_di[7:0] <= rx_byte;
                                ram_we <= 1;
-                               state <= |words_left ? `STATE_READ1 : `STATE_IDLE;
+                               if(|words_left) begin
+                                  state <= `STATE_READ1;
+                               end else begin
+                                  state <= `STATE_IDLE;
+                                  finished <= 1;
+                               end
                         end
                  end
                endcase
-        end
+        end // if (clk_enable)
+        else
+          finished <= 0;
 endmodule

diff --git a/yosys-sim-script b/yosys-sim-script
index 9cffede952a7db8d46e6e4a9b1e7a326590ea9ec..10f21eca9ecd507c127ebf4655dc12afc7beca53 100755 (executable)
--- a/yosys-sim-script
+++ b/yosys-sim-script
@@ -1,3 +1,3 @@
-read_verilog -sv -DSIM flash.v
-prep -top top -nordff
-sim -clock CLK -vcd test.vcd -n 3000
+read_verilog -sv -DSIM lisp_processor.v
+prep -top cpu -nordff
+sim -clock clk -vcd test.vcd -n 3000