10 `define GCOP_CDRQ 4'd3
11 `define GCOP_CARQ 4'd4
12 `define GCOP_CARR 4'd5
13 `define GCOP_CDRRX 4'd6
14 `define GCOP_CARRX 4'd7
15 `define GCOP_CDRQX 4'd8
16 `define GCOP_CONS 4'd9
17 `define GCOP_XCONS 4'd10
18 `define GCOP_RPLACDR 4'd11
19 `define GCOP_LDQ 4'd12
20 `define GCOP_RDQ 4'd13
21 `define GCOP_RDQA 4'd14
22 `define GCOP_RDQCDRRX 4'd15
24 `define STATE_READ 3'b100
25 `define STATE_RUN 3'b010
26 `define STATE_WRITE 3'b001
29 `define START_STATE `STATE_RUN
31 `define START_STATE `STATE_READ
37 `define UART_DIVIDE 625
40 module cpu (input clk, output [4:0] led, output uart_tx, input uart_rx);
41 reg [3:0] state = `START_STATE;
43 wire is_reading = state == `STATE_READ;
44 wire is_running = state == `STATE_RUN;
45 wire is_writing = state == `STATE_WRITE;
47 wire reset = !is_running;
50 wire gc_clock_enable = is_running;
51 wire eval_clock_enable = step_eval & is_running;
52 wire reader_clock_enable = is_reading;
53 wire writer_clock_enable = is_writing;
55 always @ (posedge clk)
56 counter <= counter + 1;
70 wire [12:0] gc_ram_addr;
71 wire [15:0] gc_ram_di;
74 wire [12:0] reader_ram_addr;
75 wire [15:0] reader_ram_di;
77 wire [12:0] writer_ram_addr;
79 wire ram_we = reader_clock_enable ? reader_ram_we : gc_ram_we;
80 wire [12:0] ram_addr = reader_clock_enable ? reader_ram_addr : writer_clock_enable ? writer_ram_addr : gc_ram_addr;
81 wire [15:0] ram_di = reader_clock_enable ? reader_ram_di : gc_ram_di;
87 GCRAM gcram (.clk(clk), .we(ram_we), .addr(ram_addr), .di(ram_di), .do(ram_do));
89 GC gc (.clk(clk), .rst(reset), .clk_enable(gc_clock_enable), .Ein(E1), .Eout(E2), .gcop(gcop), .ostate(gostate), .step_eval(step_eval), .conn_ea(conn_ea), .conn_et(conn_et), .ram_we(gc_ram_we), .ram_addr(gc_ram_addr), .ram_di(gc_ram_di), .ram_do(ram_do), .Pout(P));
91 EVAL eval (.clk(clk), .rst(reset), .clk_enable(eval_clock_enable), .Ein(E2), .Eout(E1), .gcop(gcop), .ostate(eostate), .conn_ea(conn_ea), .conn_et(conn_et));
93 READER reader (.clk(clk), .clk_enable(reader_clock_enable), .rx_byte(uart_rx_byte), .rx_signal(uart_rx_signal), .finished(reader_finished), .ram_we(reader_ram_we), .ram_addr(reader_ram_addr), .ram_di(reader_ram_di));
95 WRITER writer (.clk(clk), .clk_enable(writer_clock_enable), .tx_byte(uart_tx_byte), .tx_signal(uart_tx_signal), .tx_busy(uart_is_transmitting), .finished(writer_finished), .ram_addr(writer_ram_addr), .ram_do(ram_do), .P(P));
99 wire [7:0] uart_rx_byte;
100 wire uart_is_receiving;
101 wire uart_is_transmitting;
106 wire [7:0] uart_tx_byte;
108 always @ (posedge clk) begin
109 if(is_writing & writer_finished)
110 state <= `STATE_READ;
112 if(is_reading & reader_finished)
115 if(is_running & eostate == 5'd7)
116 state <= `STATE_WRITE;
120 uart #(.CLOCK_DIVIDE(`UART_DIVIDE)) uart (.clk(clk), .rx(uart_rx), .tx(uart_tx), .transmit(uart_tx_signal), .tx_byte(uart_tx_byte), .received(uart_rx_signal), .rx_byte(uart_rx_byte), .is_receiving(uart_is_receiving), .is_transmitting(uart_is_transmitting), .recv_error (uart_rx_error));
122 // Assign the outputs
123 assign led[0] = is_reading;
124 assign led[1] = uart_is_receiving;
125 assign led[2] = is_writing;
126 assign led[3] = uart_is_transmitting;
127 assign led[4] = is_running;