Commit | Line | Data |
---|---|---|
2ed306f8 MG |
1 | `include "gc.v" |
2 | `include "eval.v" | |
3f6eb730 | 3 | `include "reader.v" |
2ed306f8 | 4 | `include "uart.v" |
3f6eb730 | 5 | `include "writer.v" |
2ed306f8 MG |
6 | |
7 | `define GCOP_NOP 4'd0 | |
8 | `define GCOP_CDR 4'd1 | |
9 | `define GCOP_CAR 4'd2 | |
10 | `define GCOP_CDRQ 4'd3 | |
11 | `define GCOP_CARQ 4'd4 | |
12 | `define GCOP_CARR 4'd5 | |
13 | `define GCOP_CDRRX 4'd6 | |
14 | `define GCOP_CARRX 4'd7 | |
15 | `define GCOP_CDRQX 4'd8 | |
16 | `define GCOP_CONS 4'd9 | |
17 | `define GCOP_XCONS 4'd10 | |
18 | `define GCOP_RPLACDR 4'd11 | |
19 | `define GCOP_LDQ 4'd12 | |
20 | `define GCOP_RDQ 4'd13 | |
21 | `define GCOP_RDQA 4'd14 | |
22 | `define GCOP_RDQCDRRX 4'd15 | |
23 | ||
62e5ccb8 MG |
24 | `define STATE_READ 3'b100 |
25 | `define STATE_RUN 3'b010 | |
26 | `define STATE_WRITE 3'b001 | |
27 | ||
28 | `ifdef SIM | |
29 | `define START_STATE `STATE_RUN | |
30 | `else | |
31 | `define START_STATE `STATE_READ | |
32 | `endif | |
33 | ||
3f6eb730 MG |
34 | `ifdef SIM |
35 | `define UART_DIVIDE 1 | |
36 | `else | |
eb54e6d0 | 37 | `define UART_DIVIDE 625 |
3f6eb730 MG |
38 | `endif |
39 | ||
eba93362 | 40 | module cpu (input clk, output [4:0] led, output uart_tx, input uart_rx); |
62e5ccb8 | 41 | reg [3:0] state = `START_STATE; |
b5efed3a | 42 | |
62e5ccb8 MG |
43 | wire is_reading = state == `STATE_READ; |
44 | wire is_running = state == `STATE_RUN; | |
45 | wire is_writing = state == `STATE_WRITE; | |
2ed306f8 | 46 | |
62e5ccb8 MG |
47 | wire reset = !is_running; |
48 | reg counter = 0; | |
2ed306f8 | 49 | |
62e5ccb8 MG |
50 | wire gc_clock_enable = is_running; |
51 | wire eval_clock_enable = step_eval & is_running; | |
52 | wire reader_clock_enable = is_reading; | |
53 | wire writer_clock_enable = is_writing; | |
2ed306f8 MG |
54 | |
55 | always @ (posedge clk) | |
56 | counter <= counter + 1; | |
57 | ||
eb54e6d0 | 58 | wire [12:0] P; |
b5efed3a MG |
59 | wire [15:0] E1; |
60 | wire [15:0] E2; | |
2ed306f8 MG |
61 | wire [3:0] gcop; |
62 | wire [5:0] gostate; | |
63 | wire [5:0] eostate; | |
64 | wire conn_ea; | |
65 | wire conn_et; | |
66 | ||
67 | wire step_eval; | |
68 | ||
3f6eb730 MG |
69 | wire gc_ram_we; |
70 | wire [12:0] gc_ram_addr; | |
71 | wire [15:0] gc_ram_di; | |
72 | ||
73 | wire reader_ram_we; | |
74 | wire [12:0] reader_ram_addr; | |
75 | wire [15:0] reader_ram_di; | |
76 | ||
77 | wire [12:0] writer_ram_addr; | |
78 | ||
62e5ccb8 MG |
79 | wire ram_we = reader_clock_enable ? reader_ram_we : gc_ram_we; |
80 | wire [12:0] ram_addr = reader_clock_enable ? reader_ram_addr : writer_clock_enable ? writer_ram_addr : gc_ram_addr; | |
81 | wire [15:0] ram_di = reader_clock_enable ? reader_ram_di : gc_ram_di; | |
44b73af5 MG |
82 | wire [15:0] ram_do; |
83 | ||
62e5ccb8 | 84 | wire reader_finished; |
3f6eb730 | 85 | wire writer_finished; |
3f6eb730 | 86 | |
eb54e6d0 | 87 | GCRAM gcram (.clk(clk), .we(ram_we), .addr(ram_addr), .di(ram_di), .do(ram_do)); |
44b73af5 | 88 | |
eb54e6d0 | 89 | GC gc (.clk(clk), .rst(reset), .clk_enable(gc_clock_enable), .Ein(E1), .Eout(E2), .gcop(gcop), .ostate(gostate), .step_eval(step_eval), .conn_ea(conn_ea), .conn_et(conn_et), .ram_we(gc_ram_we), .ram_addr(gc_ram_addr), .ram_di(gc_ram_di), .ram_do(ram_do), .Pout(P)); |
3f6eb730 MG |
90 | |
91 | EVAL eval (.clk(clk), .rst(reset), .clk_enable(eval_clock_enable), .Ein(E2), .Eout(E1), .gcop(gcop), .ostate(eostate), .conn_ea(conn_ea), .conn_et(conn_et)); | |
2ed306f8 | 92 | |
62e5ccb8 | 93 | READER reader (.clk(clk), .clk_enable(reader_clock_enable), .rx_byte(uart_rx_byte), .rx_signal(uart_rx_signal), .finished(reader_finished), .ram_we(reader_ram_we), .ram_addr(reader_ram_addr), .ram_di(reader_ram_di)); |
3f6eb730 | 94 | |
5284821b | 95 | WRITER writer (.clk(clk), .clk_enable(writer_clock_enable), .tx_byte(uart_tx_byte), .tx_signal(uart_tx_signal), .tx_busy(uart_is_transmitting), .finished(writer_finished), .ram_addr(writer_ram_addr), .ram_do(ram_do), .P(P)); |
2ed306f8 MG |
96 | |
97 | // UART outputs | |
98 | wire uart_rx_signal; | |
99 | wire [7:0] uart_rx_byte; | |
100 | wire uart_is_receiving; | |
101 | wire uart_is_transmitting; | |
102 | wire uart_rx_error; | |
103 | ||
2ed306f8 | 104 | // UART logic |
3f6eb730 MG |
105 | wire uart_tx_signal; |
106 | wire [7:0] uart_tx_byte; | |
107 | ||
108 | always @ (posedge clk) begin | |
62e5ccb8 MG |
109 | if(is_writing & writer_finished) |
110 | state <= `STATE_READ; | |
111 | ||
112 | if(is_reading & reader_finished) | |
113 | state <= `STATE_RUN; | |
114 | ||
115 | if(is_running & eostate == 5'd7) | |
116 | state <= `STATE_WRITE; | |
3f6eb730 | 117 | end |
2ed306f8 | 118 | |
eb54e6d0 | 119 | // 4800 baud uart |
3f6eb730 | 120 | uart #(.CLOCK_DIVIDE(`UART_DIVIDE)) uart (.clk(clk), .rx(uart_rx), .tx(uart_tx), .transmit(uart_tx_signal), .tx_byte(uart_tx_byte), .received(uart_rx_signal), .rx_byte(uart_rx_byte), .is_receiving(uart_is_receiving), .is_transmitting(uart_is_transmitting), .recv_error (uart_rx_error)); |
2ed306f8 MG |
121 | |
122 | // Assign the outputs | |
62e5ccb8 MG |
123 | assign led[0] = is_reading; |
124 | assign led[1] = uart_is_receiving; | |
125 | assign led[2] = is_writing; | |
126 | assign led[3] = uart_is_transmitting; | |
127 | assign led[4] = is_running; | |
2ed306f8 | 128 | endmodule |