[clump.git] / yosys-sim-script

read_verilog -sv -DSIM toplevel.v
prep -top cpu -nordff
sim -clock clk -vcd test.vcd -n 3000
Commit	Line	Data
23c26e04	1	read_verilog -sv -DSIM toplevel.v
62e5ccb8 MG	2	prep -top cpu -nordff
62e5ccb8 MG	3	sim -clock clk -vcd test.vcd -n 3000