master.v

   1 `include "master_rom.v"
   2
   3 `ifdef SIM
   4  `define UART_DIVIDE 1
   5 `else
   6  `define UART_DIVIDE 1
   7  // s/192/3/ for 19200 baud uart
   8 `endif
   9
  10 module master(input CLKin, output [4:0] led, output uart_tx, input uart_rx, output reg ready_out = 1, input ready_in);
  11    wire clk;
  12    wire clk_tmp;
  13
  14    //pll pll (.clock_in(CLKin), .clock_out(clk));
  15
  16    reg [20:0] counter = 0;
  17
  18    reg            clk = 0;
  19
  20    always @ (posedge CLKin) begin
  21           if(counter == 5000) begin
  22                  counter <= 0;
  23                  clk <= 1 - clk;
  24           end
  25           else
  26                 counter <= counter + 1;
  27    end
  28
  29    reg [4:0] program_counter = 0;
  30    wire [63:0] rom_output;
  31
  32    master_rom master_rom (.clk(clk), .addr(program_counter), .data(rom_output));
  33
  34
  35 `define STATE_SEND 0
  36 `define STATE_WAIT_PROPAGATE 1
  37 `define STATE_WAIT_NEWS 2
  38
  39    reg [5:0] state = `STATE_SEND;
  40    reg [5:0] uart_ptr = 0;
  41
  42    wire            received;
  43    wire [7:0]  rx_byte;
  44    reg             transmit = 0;
  45    reg  [7:0]  tx_byte = 0;
  46    wire            is_receiving;
  47    wire            is_transmitting;
  48
  49    // 19200 (actually 300) baud uart
  50    uart #(.CLOCK_DIVIDE(`UART_DIVIDE)) uart (.clk(clk), .rx(uart_rx), .tx(uart_tx), .received(received), .transmit(transmit), .tx_byte(tx_byte), .rx_byte(rx_byte), .is_receiving(is_receiving), .is_transmitting(is_transmitting));
  51
  52    always @(posedge clk) begin
  53           case(state)
  54                 `STATE_SEND: begin
  55                    if(transmit) begin
  56                           transmit <= 0;
  57                    end else if(uart_ptr == 4) begin
  58                           program_counter <= program_counter + 1;
  59                           uart_ptr <= 0;
  60                           state <= `STATE_WAIT_PROPAGATE;
  61                    end else if(!is_transmitting && ready_in) begin
  62                           tx_byte <= rom_output[uart_ptr * 8 +: 8];
  63                           transmit <= 1;
  64                           uart_ptr <= uart_ptr + 1;
  65                    end
  66                 end
  67
  68                 `STATE_WAIT_PROPAGATE: begin
  69                    if(received) begin
  70                           state <= `STATE_SEND;
  71                    end
  72                 end
  73
  74                 `STATE_WAIT_NEWS: begin
  75
  76                 end
  77           endcase
  78    end
  79
  80 endmodule