writer.v

   1 `define STATE_START        2'b00
   2 `define STATE_WRITE1       2'b01
   3 `define STATE_WRITE2       2'b10
   4 `define STATE_INCREMENT    2'b11
   5
   6 module WRITER (input clk, input clk_enable, output reg [7:0] tx_byte, output reg tx_signal = 0, input tx_busy, output reg finished = 0, output [12:0] ram_addr, input [15:0] ram_do, input [12:0] freeptr);
   7    reg [1:0] state = `STATE_START;
   8
   9    reg [12:0] current_index;
  10
  11    assign ram_addr = current_index;
  12
  13    always @ (posedge clk) begin
  14          if (clk_enable) begin
  15                 if(tx_signal)
  16                   tx_signal <= 0;
  17
  18                 case(state)
  19                   `STATE_START: begin
  20                          current_index <= 4;
  21                          state <= `STATE_WRITE1;
  22                   end
  23
  24                   `STATE_WRITE1: begin
  25                          if(!tx_busy && !tx_signal) begin
  26                                 tx_signal <= 1;
  27                                 tx_byte <= ram_do[15:8];
  28                                 state <= `STATE_WRITE2;
  29                          end
  30                   end
  31
  32                   `STATE_WRITE2: begin
  33                          if(!tx_busy && !tx_signal) begin
  34                                 tx_signal <= 1;
  35                                 tx_byte <= ram_do[7:0];
  36                                 state <= `STATE_INCREMENT;
  37                          end
  38                   end
  39
  40                   `STATE_INCREMENT: begin
  41                          current_index <= current_index + 1;
  42                          if(current_index >= freeptr) begin
  43                                 finished <= 1;
  44                                 state <= `STATE_START;
  45                          end else begin
  46                                 state <= `STATE_WRITE1;
  47                          end
  48                   end
  49                 endcase // case (state)
  50          end // if (clk_enable)
  51          else
  52            finished <= 0;
  53    end
  54 endmodule