reader.v

   1 `define STATE_IDLE    2'd0
   2 `define STATE_LENGTH  2'd1
   3 `define STATE_READ1   2'd2
   4 `define STATE_READ2   2'd3
   5
   6 module READER (input clk, input clk_enable, input [7:0] rx_byte, input rx_signal, output reg finished = 0, output reg ram_we, output [12:0] ram_addr, output reg [15:0] ram_di);
   7    reg [1:0] state = `STATE_IDLE;
   8
   9    reg [12:0] total_words;
  10    reg [12:0] current_index;
  11
  12    assign ram_addr = current_index;
  13
  14    always @ (posedge clk)
  15          if (clk_enable) begin
  16                 if(!rx_signal) ram_we <= 0;
  17
  18                 case(state)
  19                   `STATE_IDLE: begin
  20                          if(rx_signal) begin
  21                                 total_words[12:8] <= rx_byte[4:0];
  22                                 current_index <= -1;
  23                                 state <= `STATE_LENGTH;
  24                          end
  25                   end
  26
  27                   `STATE_LENGTH: begin
  28                          if(rx_signal) begin
  29                                 total_words[7:0] <= rx_byte;
  30                                 state <= `STATE_READ1;
  31                          end
  32                   end
  33
  34                   `STATE_READ1: begin
  35                          if(rx_signal) begin
  36                                 ram_di[15:8] <= rx_byte;
  37                                 current_index <= current_index + 1;
  38                                 state <= `STATE_READ2;
  39                          end
  40                   end
  41
  42                   `STATE_READ2: begin
  43                          if(rx_signal) begin
  44                                 ram_di[7:0] <= rx_byte;
  45                                 ram_we <= 1;
  46                                 if(current_index == total_words) begin
  47                                    state <= `STATE_READ1;
  48                                 end else begin
  49                                    state <= `STATE_IDLE;
  50                                    finished <= 1;
  51                                 end
  52                          end
  53                   end
  54                 endcase
  55          end // if (clk_enable)
  56          else
  57            finished <= 0;
  58 endmodule