Slightly simpler reader

diff --git a/reader.v b/reader.v
index 88e52e71bcf730f7c8a6652304585a64b20271ae..e96131e9b9645b72009278b7c30b0793ca0fb16d 100644 (file)
--- a/reader.v
+++ b/reader.v
@@ -6,7 +6,7 @@
 module READER (input clk, input clk_enable, input [7:0] rx_byte, input rx_signal, output reg finished = 0, output reg ram_we, output [12:0] ram_addr, output reg [15:0] ram_di);
    reg [1:0] state = `STATE_IDLE;
 
-   reg [12:0] words_left;
+   reg [12:0] total_words;
    reg [12:0] current_index;
 
    assign ram_addr = current_index;
@@ -18,8 +18,7 @@ module READER (input clk, input clk_enable, input [7:0] rx_byte, input rx_signal
                case(state)
                  `STATE_IDLE: begin
                         if(rx_signal) begin
-                               words_left[12:8] <= rx_byte[4:0];
-                               words_left[7:0] <= 0;
+                               total_words[12:8] <= rx_byte[4:0];
                                current_index <= -1;
                                state <= `STATE_LENGTH;
                         end
@@ -27,7 +26,7 @@ module READER (input clk, input clk_enable, input [7:0] rx_byte, input rx_signal
 
                  `STATE_LENGTH: begin
                         if(rx_signal) begin
-                               words_left[7:0] <= rx_byte;
+                               total_words[7:0] <= rx_byte;
                                state <= `STATE_READ1;
                         end
                  end
@@ -36,7 +35,6 @@ module READER (input clk, input clk_enable, input [7:0] rx_byte, input rx_signal
                         if(rx_signal) begin
                                ram_di[15:8] <= rx_byte;
                                current_index <= current_index + 1;
-                               words_left <= words_left - 1;
                                state <= `STATE_READ2;
                         end
                  end
@@ -45,7 +43,7 @@ module READER (input clk, input clk_enable, input [7:0] rx_byte, input rx_signal
                         if(rx_signal) begin
                                ram_di[7:0] <= rx_byte;
                                ram_we <= 1;
-                               if(|words_left) begin
+                               if(current_index == total_words) begin
                                   state <= `STATE_READ1;
                                end else begin
                                   state <= `STATE_IDLE;