writer.v

   1 `define STATE_START        2'b00
   2 `define STATE_WRITE1       2'b01
   3 `define STATE_WRITE2       2'b10
   4 `define STATE_INCREMENT    2'b11
   5
   6 module WRITER (input clk, input clk_enable, output reg [7:0] tx_byte, output reg tx_signal = 0, input tx_busy, output reg finished = 0, output [12:0] ram_addr, input [15:0] ram_do, input [12:0] P);
   7    reg [1:0] state = `STATE_START;
   8
   9    reg [12:0] current_index;
  10    reg [12:0] freeptr;
  11
  12    assign ram_addr = current_index;
  13
  14    always @ (posedge clk) begin
  15          if (clk_enable) begin
  16                 if(tx_signal)
  17                   tx_signal <= 0;
  18
  19                 case(state)
  20                   `STATE_START: begin
  21                          finished <= 0;
  22                          current_index <= 4;
  23                          freeptr <= P;
  24                          state <= `STATE_WRITE1;
  25                   end
  26
  27                   `STATE_WRITE1: begin
  28                          if(!tx_busy && !tx_signal) begin
  29                                 tx_signal <= 1;
  30                                 tx_byte <= ram_do[15:8];
  31                                 state <= `STATE_WRITE2;
  32                          end
  33                   end
  34
  35                   `STATE_WRITE2: begin
  36                          if(!tx_busy && !tx_signal) begin
  37                                 tx_signal <= 1;
  38                                 tx_byte <= ram_do[7:0];
  39                                 state <= `STATE_INCREMENT;
  40                          end
  41                   end
  42
  43                   `STATE_INCREMENT: begin
  44                          current_index <= current_index + 1;
  45                          if(current_index >= freeptr) begin
  46                                 finished <= 1;
  47                                 state <= `STATE_START;
  48                          end else begin
  49                                 state <= `STATE_WRITE1;
  50                          end
  51                   end
  52                 endcase // case (state)
  53          end // if (clk_enable)
  54          else
  55            finished <= 0;
  56    end
  57 endmodule